NVIDIA2016PhysicalDesign笔试

1、NVIDIA Confidential SH-05-A-ASIC PDNVIDIA 2016 Campus RecruitmentExam Test Paper SH-05-A-ASIC PDCover PageTotal pages: 12Exam Duration: 120 minutes* Please answer all the questions in EnglishApplied Position: ASIC Physical Design Engineer Candidate Chinese Full Name/中文名Candidate School Name/毕业学校Cand

2、idate ID Number/身份证号Candidate Contact Number/手机号码Candidate E-mail address/邮箱地址Current Degree/学历Bachelor / Master / PhD *Graduation Time/毕业时间 / (Year/ Month)Major/专业The two questions below are used only for reference, they are not criteria for hiring. Please fill in accurately.(以下两问题仅作为参考信息，不作为新员工录用标

3、准, 请如实填写)Availability for Internship before graduation/毕业前能否作实习生(Yes/No)  When will be available for internship/何时可以开始实习 考生守则&注意事项：1. 请确认你的座位上的标签与你的姓名，座位编号及所应考的职位符合；试卷首页最上方应该是你在网上申请职位的名称，请确认这个职位是你在网上申请的第一志愿的职位，如果不是，请举手告诉监考人员；2. 请检查试卷是否有漏页，总页数请参考试卷封面；3. 试卷封面所有信息须由中文填写，试卷封面上需要选择你投递职位的勾选框

4、，请一定要进行勾选；试题部分请用英文作答；答题尽量写在试题下方的空白处，如果写不下，再使用附页，但须在题目下方进行注明；4. 考试期间，如有发问，请举手, 如果你需要更多的草稿纸，请举手通知监考员；5. 除了贵重物品随身携带之外，请确认你把你的随行物品放在包包里面，并把你的包包放在课室的最前方；6. 桌上只准放文具，计算机，简历及身份证；把你的身份证及简历放在桌上的右上角，在开考后监考员会查阅7. 请关闭所有手机和移动设备，如果你的手机响起来，你将会被取消考试资格；如果需要了解时间情况，请联系你身边的监考人员；8. 开考30分钟以后不允许进场。请注意黑板上所写的试卷种类，并请核对确认自己所答试

5、卷的考试时间，这个时间应该与你试卷上的时间一致。监考人员会在考试结束的前15分钟、5分钟之时提醒大家。请注意你的考卷封面的说明，如果你拿到的试卷要求用英文作答，请一定要按照要求作答。如果你完成考卷，可以选择在开考之后一小时后提早离开，但不可以在收卷之前十五分钟离 开考场，监考员届时会有所宣布(60min考试的同学不能提前离开考场；90分钟考试的同学可以在15：00-15：15pm之间离开；120分钟考试的同学可以在15：00-15：45pm之间离开)；否则你会被视为违反考场纪律；9. 如果你选择提早离开，请举手通知监考员，将你的试卷和简历倒扣在桌面上，并携带所有带来的物品，离开时请保持安静；1

6、0. 离开时不准携带任何的纸张，包括考卷与草稿纸，否则，你将会被取消资格；11. 考试结束后，笔试通过的同学，在两个星期之内，会收到我们的电话通知及安排面试，请留意电话来电；12. 考生必须严格遵守考试纪律，请一定诚实作答，不准交头接耳或左顾右盼，不准向其他考生作暗示，不准偷看、夹带、代考，不准抄袭他人答案或有意将自己的答案让他人抄袭，不准接传答案或交换试卷或任何纸张；13. 考卷是NVIDIA的专利财产之一， 考生严禁在考试后泄露试题。1. Use basic logic gates to implement below RTL code.Available gates: AND/DFF/N

7、OT/ORModule test_logic_1 (A,B,rst_n,clk,Y);input A;input B;input clk;input rst_n;output Y;reg Y;wire gate_en;assigngate_en = A * B;always (posedge clk or negedge rst_n)if (!rst_n)beginY<=1b0;endelse if (gate_en)beginY <= A;endendmodule2. Suppose you have a file, named "vio.txt", that

8、 list 100 timing violations after running STA,  those violations have different attributes, like corners(PVT) and type(setup, hold).  The file format see below, you need to write scripts to analysis the violations status from "vio.txt". <<vio.txt>>: #VioID:  

9、;        corner                    type               slack  Vio1:    

10、          ssg_0c_0p6v        setup              -0.01 Vio2:              ffg_105c_0p72v

11、60; hold                -0.2 Vio100:          ffg_0c_0p99v      setup             -0.04A) 

12、  Get the total setup and hold violation numbers.B)   Get the worst slack of hold violation in each corner.   3. List some methods to decrease power in physical design.4. Please describe the cause reason of metastability in digital circuit design, and how to reduce the possi

13、bility of failure due to metastability.5. Please respectively sort according to the cell delay and leakage power for cell HVT(high vt), SVT (standard vt), LVT (low vt). And whats the problem if we use too many LVT cells in a small area?6. Decide which one is the correct expression for the following

14、pic. a) Y = (!(A1|(!A2)|(!B1)&&B2);b) Y = (!(A1&&(!A2)|(!B1)&&B2);c) Y = (!(A1&&(!A2)&&(!B1)&&B2);d) Y = (!(A1&&(!A2)&&(!B1)|B2);7. There is one path as below:The clock definition is as below:create_clock period 2 name CLK get_ports CLK

15、 waveform 0 1create_generated_clock -name CLKP -edges 2 3 4 -source CLK get_pins CLKPcreate_generated_clock -name CLKM -edges 2 6 10 -source CLK get_pins CLKMPlease draw the waveform picture to show the setup and hold timing check before and after add below exception:set_multicycle_path 2 -setup -fr

16、om get_clocks CLKP -to get_clocks CLKM -startset_multicycle_path 1 -hold -from get_clocks CLKP -to get_clocks CLKM -start8. Please take a look with below path.a) Is it setup violation path or hold violation path? How to identify with it?b) How to fix such violations? (please list 3 ways )Startpoint:

17、 r_nv_ram_rw_18x39_fifola/Ra_reg_r0_reg/Q_reg_2_ (rising edge-triggered flip-flop clocked by xclk)Endpoint: pior1_in_orpix_pd_reg_31_dff_11_ (rising edge-triggered flip-flop clocked by xclk)Path Group: xclkPath Type: maxPoint Fanout Cap DTrans Trans Delta Incr Path-clock xclk (rise edge) 0.000 0.000

18、clock network delay (propagated) 0.636 0.636r_nv_ram_rw_18x39_fifola/Ra_reg_r0_reg/Q_reg_2_/CP (SDFQD1PO3) 0.025 0.000 0.636 rr_nv_ram_rw_18x39_fifola/Ra_reg_r0_reg/Q_reg_2_/Q (SDFQD1PO3) 0.146 0.193 & 0.829 fr_nv_ram_rw_18x39_fifola/Ra_reg_r02 (net) 6 0.021 r_nv_ram_rw_18x39_fifola/U297/A2 (NR2

19、D1) 0.040 0.147 0.014 0.021 & 0.851 fr_nv_ram_rw_18x39_fifola/U297/ZN (NR2D1) 0.083 0.104 & 0.955 rr_nv_ram_rw_18x39_fifola/n209 (net) 2 0.004 r_nv_ram_rw_18x39_fifola/U155/A2 (ND3D1) 0.004 0.083 0.002 0.002 & 0.957 rr_nv_ram_rw_18x39_fifola/U155/ZN (ND3D1) 0.119 0.096 & 1.052 fr_nv_

20、ram_rw_18x39_fifola/n210 (net) 4 0.005 r_nv_ram_rw_18x39_fifola/U702/A2 (NR2D2) 0.013 0.119 0.005 0.005 & 1.057 fr_nv_ram_rw_18x39_fifola/U702/ZN (NR2D2) 0.364 0.245 & 1.302 rr_nv_ram_rw_18x39_fifola/n663 (net) 32 0.052 r_nv_ram_rw_18x39_fifola/U775/A1 (AOI22D0P5HVT) 0.020 0.366 0.008 0.020

21、& 1.322 rr_nv_ram_rw_18x39_fifola/U775/ZN (AOI22D0P5HVT) 0.206 0.275 & 1.597 fr_nv_ram_rw_18x39_fifola/n235 (net) 1 0.003 r_nv_ram_rw_18x39_fifola/U774/A4 (ND4D1) 0.103 0.206 0.037 0.038 & 1.635 fr_nv_ram_rw_18x39_fifola/U774/ZN (ND4D1) 0.062 0.088 & 1.722 rr_nv_ram_rw_18x39_fifola/n

22、239 (net) 1 0.002 r_nv_ram_rw_18x39_fifola/U773/C (AOI211D1) 0.007 0.062 0.003 0.003 & 1.725 rr_nv_ram_rw_18x39_fifola/U773/ZN (AOI211D1) 0.177 0.074 & 1.799 fr_nv_ram_rw_18x39_fifola/n241 (net) 1 0.010 r_nv_ram_rw_18x39_fifola/U123/A3 (CKND3D1) 0.046 0.177 0.017 0.019 & 1.818 fr_nv_ram_

23、rw_18x39_fifola/U123/ZN (CKND3D1) 0.263 0.232 & 2.051 rpior1_in_h1_fifo_rd_data_d11 (net) 2 0.014 U9855/B2 (AO2222D2) 0.174 0.263 0.061 0.064 & 2.114 rU9855/Z (AO2222D2) 0.035 0.156 & 2.270 rpior1_in_N13 (net) 1 0.002 pior1_in_orpix_pd_reg_31_dff_11_/D (SDFQSC2D1HVT) 0.004 0.035 0.002 0.002 & 2.271 rdata arrival time 2.271clock xclk (rise edge) 1.680 1.680clock network delay (propagated) 0.628 2.308clock reconvergence pessimism 0.024 2.331clock uncertainty -0.010 2.321pior1_in_orpix_pd_reg_31_dff_11_/CP (SDFQSC2D1HVT) 2.321 rlibrary setup time