EDA实现电子琴的程序

1、精选文档实验十五 电子琴设计一、 音名与频率的关系：音乐上的十二平均律规定：每两个八度音之间的频率相差一倍。在这两个八度音之间，分成十二个半音，每两个相邻伴音的频率比为12Ö2。另外还规定，音名A的频率为440Hz。音名B到C、E到F之间为半音，其余为全音。这样，可计算得从A（简谱的低音6）到a1（简谱的高音6）之间每个音名的频率为：A（6）：440Hza（6）：880Hza1（6）：1760HzB（7）：493.88Hzb（7）：987.76Hzc（1）：523.25Hzc1（1）：1046.50Hz d（2）：587.33Hzd1（2）：1174.66Hze（3）：659.25H

2、ze1（3）：1318.51Hzf（4）：698.46Hzf1（4）：1396.92Hzg（5）：783.99Hzg1（5）：1567.98Hz二、设计要求：设计一个电子琴，要求能演奏音名A到a1之间的全部音阶。按下一个键，则演奏该音名，并用数码管显示音名，用发光二极管指示高、中、低音。三、设计提示：本实验由键盘编码，音频输出译码器、分频器组成。取10MHz信号作为基准。以基准频率除以上述频率，可得各音名频率的分频系数。注意，为了减少输出的偶次谐波成分，最后输出应为对称方波。音频输出译码器实质上是一个多路选择器，根据键盘编码的输出，选择音阶发生器的不同的预置数，分频后输出音频。分频器可以为加法

3、计数器，以可以为减法计数器，计算预置数时稍有不同，应加以注意。另外，应根据基准频率和输出频率，来确定计数器的位数。设计框图如下图所示：按键编码预置数选择可预置计数器T触发器（二分频）扫描时钟按键输入键码10MHz时钟音频输出预置数译码器显示输出电子琴框图四、实验步骤1、启动ISE集成开发环境，创建工程并输入设计源文件。2、对设计进行时序仿真，分析设计的正确性。3、锁定引脚，完成设计实现过程。并在实验箱上连线，利用iMPACT进行程序下载。4、在实验箱上验证电子琴的功能，观察并记录实验结果.五、实验报告1.music的VHDL 源程序：library ieee;use ieee.std_logi

4、c_1164.all;entity music isport(kin: std_logic_vector(0 to 15); spk_out: out std_logic; led_out: out std_logic_vector(6 downto 0); index: out std_logic_vector(2 downto 0); clk: in std_logic);end music;architecture stru of music iscomponent tonetab port( index : in INTEGER range 0 to 15; tone : out IN

5、TEGER range 0 to 16#3fff#; code : out INTEGER range 0 to 15; high : out STD_LOGIC_VECTOR(2 DOWNTO 0) );end component;component tonegen port( clk : in STD_LOGIC; tone : in integer range 0 to 16#3fff#; spks : out STD_LOGIC );end component;component hex2led port( hex : in integer range 0 to 15; led : o

6、ut STD_LOGIC_VECTOR(6 downto 0) );end component;component keybord port( kin : in STD_LOGIC_VECTOR(0 to 15);kout : out INTEGER range 0 to 15 );end component;signal kout: integer range 0 to 15;signal tone: INTEGER range 0 to 16#3fff#;signal digit: integer range 0 to 15;begin u1: keybord port map (kin=

7、>kin,kout=>kout); u2: tonetab port map (index=>kout,tone=>tone,code=>digit,high=>index); u3: tonegen port map (clk=>clk,tone=>tone,spks=>spk_out); u4: hex2led port map (hex=>digit,led=>led_out);end stru;2. hex2led的VHDL 源程序 library IEEE;use IEEE.STD_LOGIC_1164.all;ent

8、ity hex2led is port( hex : in integer range 0 to 15; led : out STD_LOGIC_VECTOR(6 downto 0) );end hex2led;architecture rtl of hex2led issignal data : std_logic_vector(6 downto 0);beginled<=not data; with hex select data<= "1111001" when 1, -1 "0100100" when 2, -2 "0110

9、000" when 3, -3 "0011001" when 4, -4 "0010010" when 5, -5 "0000010" when 6, -6 "1111000" when 7, -7 "0000000" when 8, -8 "0010000" when 9, -9 "0001000" when 10, -A "0000011" when 11, -b "1000110" when 12,

10、-C "0100001" when 13, -d "0000110" when 14, -E "0001110" when 15, -F "1000000" when others; -0end rtl;3. keybord 的VHDL 源程序 library IEEE;use IEEE.STD_LOGIC_1164.all;entity keybord is port( kin : in STD_LOGIC_VECTOR(0 to 15);kout : out INTEGER range 0 to 15 );en

11、d keybord;architecture rtl of keybord issignal data:std_logic_vector(0 to 15);begindata<=kin;process(data)beginif data(0)='0' then kout<=0;elsif data(1)='0' then kout<=1;elsif data(2)='0' then kout<=2;elsif data(3)='0' then kout<=3;elsif data(4)='0&

12、#39; then kout<=4;elsif data(5)='0' then kout<=5;elsif data(6)='0' then kout<=6;elsif data(7)='0' then kout<=7;elsif data(8)='0' then kout<=8;elsif data(9)='0' then kout<=9;elsif data(10)='0' then kout<=10;elsif data(11)='0'

13、; then kout<=11;elsif data(12)='0' then kout<=12;elsif data(13)='0' then kout<=13;elsif data(14)='0' then kout<=14;elsif data(15)='0' then kout<=15;else NULL;end if;end process;end rtl;4. tonegen的VHDL源程序 library IEEE;use IEEE.STD_LOGIC_1164.all;entity t

14、onegen is port( clk : in STD_LOGIC; tone : in integer range 0 to 16#3fff#; spks : out STD_LOGIC );end tonegen;architecture rtl of tonegen issignal fullspks:std_logic;begingenspks:process(clk,tone)variable count14: integer range 0 to 16#3fff#;-std_logic_vector(0 to 13);beginif clk'event and clk=&

15、#39;1' thenif count14=16#3fff# then -"111111111111111" thencount14:=tone;fullspks<='1'elsecount14:=count14+1;fullspks<='0'end if;end if;end process;delayspks:process(fullspks)variable count2:std_logic;beginif fullspks'event and fullspks='1' thencount2:

16、=not count2;end if;spks<=count2;end process;end rtl;5. tonetab 的VHDL源程序library IEEE;use IEEE.STD_LOGIC_1164.all;entity tonetab is port( index : in INTEGER range 0 to 15; tone : out INTEGER range 0 to 16#3fff#; code : out INTEGER range 0 to 15; high : out STD_LOGIC_VECTOR(2 DOWNTO 0) );end tonetab

17、;architecture rtl of tonetab isbeginprocess(index)begincase index iswhen 0 =>tone<=5021;code<=6;high<="100"when 1 =>tone<=6262;code<=7;high<="100"when 2 =>tone<=6829;code<=1;high<="010"when 3 =>tone<=7872;code<=2;high<=&qu

18、ot;010"when 4 =>tone<=8801;code<=3;high<="010"when 5 =>tone<=9226;code<=4;high<="010"when 6 =>tone<=10007;code<=5;high<="010"when 7 =>tone<=10703;code<=6;high<="010"when 8 =>tone<=11323;code<=7;high

19、<="010"when 9 =>tone<=11607;code<=1;high<="001"when 10 =>tone<=12129;code<=2;high<="001"when 11 =>tone<=12593;code<=3;high<="001"when 12 =>tone<=12805;code<=4;high<="001"when 13 =>tone<=13196;c

20、ode<=5;high<="001"when 14 =>tone<=13544;code<=6;high<="001"when 15 =>tone<=16383;code<=0;high<="001"when OTHERS=>NULL;end case;end process;end rtl;实验记录：1、 设计记录表，记录引脚锁定与连线情况。ISE软件实验箱端口名称芯片引脚号IO类型编号clkB4InputIO1index<0>F9OutputIO13index<1>E9OutputIO14index<2>D11OutputIO15kin<0>A4InputIO2kin<1>D5InputIO3ki