硬件结构设计

1、目录摘要：3硬件结构设计原理：4原理图：5管脚图：6微程序控制操作方法：9微程序：10Romc改编代码10data_bus改编代码12摘要：本次实验的功能是进行两个4位数的加法运算，并进行结果输出。在本次实验中，我们用到data_bus作为总线进行传输，reg_74373作为寄存器进行数据的存储，alu_74181进行加法运算。romc作为译码器进行初始状态的设定。通过这个加法器的设计，能够对硬件结构设计有了更好的了解，同时也加深了对计算机组成原理课程的理解。硬件结构设计原理：1.把模块romc改为九位输出oen,we1,we2,gwe1,oen_n1,gwe2,oen_n2,gwe3,oen

2、_n3；2.把模块reg_74244改为四位输入Din(3 0)和四位输出Qout(3 0)；3.把模块data_bus改为四位输入data_in1(3 0),Data_in2(3 0),四位输出data_out1(3 0),data_out2(3 0),data_out3(3 0);4.把模块reg_74373改为四位输入Din(3 0)和四位输出Qout(3 0)；5.把模块alu_74181改为四位输入A(3 0),B(3 0),S(3 0),和四位输出F(3 0)6.由romc向reg_74244中分别输入两个四位二进制的数，通过九位romc微程序控制器，在进入data_bus后，两个

3、数分别被写入两个reg_74373中，再进入alu_74181进行加法运算，将运算结果输入data_bus，再由另外一个reg_74373读出。原理图：管脚图：#-CLOCK-NET clk LOC = L15;#-Atlys led output-#NET atlys_led0 LOC = U18; #Atlys LD0#NET atlys_led1 LOC = M14; #Atlys LD1#NET atlys_led2 LOC = N14; #Atlys LD2#NET atlys_led3 LOC = L14; #Atlys LD3#NET atlys_led4 LOC = M13;

4、#Atlys LD4#NET atlys_led5 LOC = D4; #Atlys LD5#NET atlys_led6 LOC = P16; #Atlys LD6#NET atlys_led7 LOC = N12; #Atlys LD7#-Atlys Switch input-#NET atlys_sw0 LOC = A10; # Atlys sw0#NET atlys_sw1 LOC = D14; # Atlys sw1#NET atlys_sw2 LOC = C14; # Atlys sw2#NET atlys_sw3 LOC = P15; # Atlys sw3#NET atlys_

5、sw4 LOC = P12; # Atlys sw4#NET atlys_sw5 LOC = R5; # Atlys sw5#NET atlys_sw6 LOC = T5; # Atlys sw6#NET atlys_sw7 LOC = E4; # Atlys sw7#-EES261 switch input-NET din0 LOC = U11; #SW20NET din1 LOC = R10; #SW19NET din2 LOC = U10; #SW18NET din3 LOC = R8; #SW17NET S0 LOC = M8; #SW16NET S1 LOC = U8; #SW15N

6、ET S2 LOC = U7; #SW14NET S3 LOC = N7; #SW13#NET C_n LOC = T6; #SW12#NET C_n_Plus LOC = R7; #SW11#NET XLXN_9 LOC = N6; #SW10#NET swt8 LOC = U5; #SW9#NET swt7 LOC = V5; #SW8#NET swt6 LOC = P7; #SW7#NET swt5 LOC = T7; #SW6#NET swt4 LOC = V6; #SW5NET s0 LOC = P8; #SW4NET s1 LOC = V7; #SW3NET s2 LOC = V8

7、; #SW2NET s3 LOC = N8; #SW1#-EES261 leds output-NET XLXN_21 LOC = U16; #LED1NET XLXN_21 LOC = U15; #LED2NET XLXN_21 LOC = U13; #LED3NET XLXN_21 LOC = M11; #LED4NET XLXN_9 LOC = R11; #LED5#NET led LOC = T12; #LED6#NET led LOC = N10; #LED7#NET led LOC = M10; #LED8#-hex7seg-# NET an LOC = V16;# NET an

8、LOC = V15;# NET an LOC = V13;# NET an LOC = N11;# NET a_to_g LOC = T8; #a# NET a_to_g LOC = V10; #b# NET a_to_g LOC = T10; #c# NET a_to_g LOC = V11; #d# NET a_to_g LOC = N9; #e # NET a_to_g LOC = P11; #f# NET a_to_g LOC = V12; #g# NET dp LOC = T11; #dp#-END-微程序控制操作方法：s0 s1 s2 s3 oen we1 we2 gwe1 oen

9、_n1 gwe2 oen_n2 gwe3 oen_n3 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 0 1 1 0微程序：Romc改编代码library IEEE; use IEEE.STD_

10、LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; entity romc is Port ( s0 : in STD_LOGIC; s1 : in STD_LOGIC; s2 : in STD_LOGIC; s3 : in STD_LOGIC; oen : out STD_LOGIC; we1 : out STD_LOGIC; we2 : out STD_LOGIC; gwe1 : out STD_LOGIC; oen_n1 : out STD_LOGIC; gwe2 : out STD_LOGIC; oen_n2: out STD_LOGIC;

11、 gwe3 : out STD_LOGIC; oen_n3 : out STD_LOGIC );end romc;architecture Behavioral of romc is signal addr : std_logic_vector(1 downto 0); -input signal rdata : std_logic_vector(3 downto 0); -outputbeginaddr rdata rdata rdata rdata rdata rdata rdata rdata rdata rdata = 000000000;end case; end process;

12、oen = rdata(0); we1 = rdata(1); we2 = rdata(2); gwe1 = rdata(3); oen_n1 = rdata(4); gwe2 = rdata(5); oen_n2 = rdata(6); gwe3 = rdata(7); oen_n3 = rdata(8);end Behavioral;data_bus改编代码- Company: - Engineer: - - Create Date: 16:56:32 03/08/2013 - Design Name: - Module Name: data_bus - Behavioral - Proj

13、ect Name: - Target Devices: - Tool versions: - Description: - Dependencies: - Revision: - Revision 0.01 - File Created- Additional Comments: -library IEEE;use IEEE.STD_LOGIC_1164.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.

14、NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity data_bus is Port ( clk : in STD_LOGIC; data_in1 : in STD_LOGIC_VECTOR (3 downto 0); data_in2 : in STD_LOGIC_VECTOR (3 downto 0); data_

15、in3 : in STD_LOGIC_VECTOR (3 downto 0); data_in4 : in STD_LOGIC_VECTOR (3 downto 0); data_out1 : out STD_LOGIC_VECTOR (3 downto 0); data_out2 : out STD_LOGIC_VECTOR (3 downto 0); data_out3 : out STD_LOGIC_VECTOR (3 downto 0); data_out4 : out STD_LOGIC_VECTOR (3 downto 0); data_io1 : inout STD_LOGIC_

16、VECTOR (3 downto 0); data_io2 : inout STD_LOGIC_VECTOR (3 downto 0); we1 : in STD_LOGIC; we2 : in STD_LOGIC; we3 : in STD_LOGIC; we4 : in STD_LOGIC; we_io1: in STD_LOGIC; we_io2: in STD_LOGIC);end data_bus;architecture Behavioral of data_bus issignal bus_data_reg : STD_LOGIC_VECTOR (3downto 0);signa

17、l out_en : STD_LOGIC;begin out_en = 0 when (we1=1 or we2=1 or we3=1 or we4=1 or we_io1 = 1 or we_io2 = 1) else 1;data_io1 = bus_data_reg when out_en = 1 else ZZZZ;data_io2 = bus_data_reg when out_en = 1 else ZZZZ;data_out1 = bus_data_reg;data_out2 = bus_data_reg;data_out3 = bus_data_reg;data_out4 = bus_data_reg; process(clk)begin if clkevent and clk = 1 then if we1 = 1 then bus_data_reg