VHDL四位全加器三种语言编程

1、四位全加器的三种语言描述方式:一：数据流描述方式libraryieee;useieee.std_logic_1164.all;entityadd1isport(a,b,cin:instd_logic;s,cout:outstd_logic);endadd1;architecturedataflowofadd1isbegins=(axorb)xorcin;cout=(axorb)andcin)or(aandb);enddataflow;二：行为描述方式libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;ent

2、ityadd22isport(a,b,cin:instd_logic;s,co:outstd_logic);endadd22;architecturedataflowofadd22issignaltmp:std_logic;beginprocess(a,b,cin)variablen:integerrange0to3;constants_vector:std_logic_vector(3downto0):=1010;constantco_vector:std_logic_vector(3downto0):=1100;beginn:=0;ifa=1thenn:=n+1;endif;ifb=1th

3、enn:=n+1;endif;ifcin=1thenn:=n+1;endif;s=s_vector(n)after10;co=co_vector(n);endprocess;enddataflow;三:结构描述方式Libraryieee;Useieee.std_logic_1164.all;Entityand_2isport(a,b:instd_logic;c:outstd_logic);Endand_2;Architecturebehaveofand_2isbeginc=(aandb);Endbehave;Libraryieee;Useieee.std_logic_1164.all;Enti

4、tyor_2isport(a,b:instd_logic;c:outstd_logic);Endor_2;Architecturebehaveofor_2isbeginc=(aorb);Endbehave;Libraryieee;Useieee.std_logic_1164.all;Entityxor_2isport(a,b:instd_logic;c:outstd_logic);Endxor_2;Architecturebehaveofxor_2isbeginc=(axorb);Endbehave;Libraryieee;Useieee.std_logic_1164.all;Entityad

5、d33isport(A,B,Cin:instd_logic;Co,S:outstd_logic);Endadd33;Architecturestructureofadd33iscomponentand_2port(a,b:instd_logic;c:outstd_logic);Endcomponent;componentor_2port(a,b:instd_logic;c:outstd_logic);Endcomponent;componentxor_2port(a,b:instd_logic;c:outstd_logic);Endcomponent;signaltmp1,tmp2,tmp3:std_logic;beginu1:xor_2portmap(A,B,tmp1);u2:and_2portmap(tmp1,Cin,tmp2);u3:xor_2portm