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1、1 Institute of RF- & OE-ICsProfessional English ReportReporter: Lin XiaojuanTeacher : Pro. Zhiqun LiContent The list of the foreign papers Overview of the foreign papers Summary23The list of the foreign periodicals-1东南大学 射频与光电集成电路研究所3SwithMurad, S.A.Z.; Pokharel, R.K.; Galal, A.I.A.; Sapawi, R.; Kan

2、aya, H.; Yoshida, K.; , An Excellent Gain Flatness 3.07.0 GHz CMOS PA for UWB Applications,Microwave and Wireless Components Letters, IEEE, vol.20, no.9, pp.510-512, Sept. 2010Rhee, W.; , Design of high-performance CMOS charge pumps in phase-locked loops ,Circuits and Systems, 1999. ISCAS 99. Procee

3、dings of the 1999 IEEE International Symposium on, vol.2, no., pp.545-548 vol.2, Jul 1999 Hao zhang, Zhiqun Li, Zhigong Wang, “ A Wideband Variable Gain differential CMOS LNA for Multi-standard Wireless LAN,” International conference on microwave and millimeter wave technology, vol.3, Apr 2008, pp.

4、1334-1337.Jinup Lim; Youngjoo Cho; Kyungsoo Jung; Jongmin Park; Joongho Choi; Jaewhui Kim; , A wide-band active-RC filter with a fast tuning scheme for wireless communication receivers,Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005, vol., no., pp. 637- 640, 18-21 Sept. 200

5、5 Ranjit Gharpurey, “A Broadband Low-Noise Front-End Amplifier for Ultra Wideband in 0.13-um CMOS,” IEEE journal of solid-state circuits, vlo.40, NO.9, Sep 2005, pp.1983-1986.4The list of the foreign periodicals-2东南大学 射频与光电集成电路研究所Murad, S.A.Z.; Pokharel, R.K.; Galal, A.I.A.; Sapawi, R.; Kanaya, H.;

6、Yoshida, K.; , An Excellent Gain Flatness 3.07.0 GHz CMOS PA for UWB Applications,Microwave and Wireless Components Letters, IEEE, vol.20, no.9, pp.510-512, Sept. 2010Rhee, W.; , Design of high-performance CMOS charge pumps in phase-locked loops ,Circuits and Systems, 1999. ISCAS 99. Proceedings of

7、the 1999 IEEE International Symposium on, vol.2, no., pp.545-548 vol.2, Jul 1999 Hao zhang, Zhiqun Li, Zhigong Wang, “ A Wideband Variable Gain differential CMOS LNA for Multi-standard Wireless LAN,” International conference on microwave and millimeter wave technology, vol.3, Apr 2008, pp. 1334-1337

8、.Jinup Lim; Youngjoo Cho; Kyungsoo Jung; Jongmin Park; Joongho Choi; Jaewhui Kim; , A wide-band active-RC filter with a fast tuning scheme for wireless communication receivers,Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005, vol., no., pp. 637- 640, 18-21 Sept. 2005 Ranjit

9、Gharpurey, “A Broadband Low-Noise Front-End Amplifier for Ultra Wideband in 0.13-um CMOS,” IEEE journal of solid-state circuits, vlo.40, NO.9, Sep 2005, pp.1983-1986.41. A 5-GHz Low Phase Noise Differential ColpittsCMOS VCOthe phase noise in the 1/f 3 region is from 1/f noise.the phase in the 1/f 2

10、region is mainly from the device white noisePMOS has lower 1/f noise than NMOSThe hot carrier effect in a PMOS transistor is typically smaller than NMOS transistor In CMOS process, the transistor 1/f noise is generally high and causes serious degradation of VCO phase noise performance.So PMOS has lo

11、wer NFmin than that of the NMOS55The design of VCO1.The Colpitts VCO core adopts only PMOS in a 0.18 um CMOS technologyCircuit schematic of the differential Colpitts CMOS voltage-controlled oscillator.66Measured oscillation frequency versus control voltage1.The measured oscillation frequency covers

12、from 4.6 to 5 GHz with control voltage from -1.4 to 1 VThe measurement of VCO2.The VCO operates from 4.6 to 5 GHz with 8.3% tuning range77Measured output power at single port and efficiency versus control voltagethe1.The output power is better than 1 dBm at single port with 50 termination at the oth

13、er port. 2.We can indicates the differential output power is better than 4 dBm3.The CMOS VCO achieves dc-to-RF conversion efficiency of better than 28% over all tuning frequency.88Measured phase noise at 1-MHz offsetThe measured phase noise is -120.42 dBc/Hz at 1 MHz offset at 5 GHz99PERFORMANCE COM

14、PARISON WITH THE PREVIOUSLY REPORTED 5-GHz VCOS. THE PHASE NOISE (PN) IS MEASURED AT 1-MHz OFFSET10102. A low-power CMOS power amplifier for ultra wideband (UWB) applications11Resistive shunt feedback for broadband matchingCarefully choose the value of RF to satisfy the input and output matching sma

15、ll RF, leads to good matching but small gain; big RF, leads to bad matching but big gainRF can be replaced of the network consisting of R, C, L 12Small signal model of a common source stageFeedback configuration13Since the circuit parameters Zin and gm,eff are frequency dependant, the characteristic

16、s of Zf will also vary accordingly over the frequency band. If the Zf plot can be reproduced using some combination of R,L or C components, perfect matching and gain conditions can be achieved.Realizations of differential input-single ended ouput PASimplified PA schematic (input stage)14Matching and

17、 small signal gainInput power versus output powerPerformance summary153. Linearization of CMOS Broadband Power Amplifiers Through Combined Multigated Transistors and Capacitance CompensationThe paper presents the development of a device-level linearization technique and its applications in broadband

18、 PA.The proposed topology firstly combines derivative transconductance superposition method and gate capacitance compensation technique, and creates a “sweet region” for suppressing third-order intermodulation (IM3) without the penalty of large power consumption16Assume that The IM product at 21-2 i

19、sSchematic of an MGTR with n transisitors in parallel17Simulated gm3 of MGTRs with different number of transistorsA distributed MGTR is formed for transconductance. The gate capacitance of each CS-NMOS transistor is compensated by means of a parallel pMOS transistor.18As the output power level incre

20、ases, the proposed amplifier achieves much better linearity than that of the conventional one, and the IM3 improvement is up to 11dB.Attributed to the IM3 suppression, the linearized amplifier can achieve a higher output power and thereby higher efficiency.4. A 310-GHz Low-Power CMOS Low-Noise Ampli

21、fier for Ultra-Wideband Communication19Transistor-level schematic of the 3-10GHz two-stage UWB LNA with current reuseThe first stage adopts a complementary topology to better achieve impedance and noise matching at a reduced current budget. The second stage, implemented by means of cascode amplifier

22、 with resonant load, aims at improving gain and reverse isolation,as well.The OTA sets both the gate voltage of M1 according to the bias current of M5 and the gate voltage of M3 to the value of the gate-source voltage of M6.20To plish the 310-GHz impedance matching, the LNA makes use of gate and sou

23、rce inductances (LG,LS) of the first stage to provide resonance at three different frequencies.Circuit model of the first LNA stage under the hypothesis that M1 and M2 are shunt connected. Simplified for the calculation of Zin.21UWB LNA input network and noise performance simulations22Measured and s

24、imulated S11 and S12Measured and simulated S21 and NFMeasured and simulated group delay and phase of S21 5. A 2.4-GHz Low-IF receiver for wideband WLAN in 0.6-um CMOS-Architecture and front-end233 selectable channel BW : 625 kHz, 2.5 MHz, and 10 MHzReceiver block diagramIt is a dual-conversion recei

25、verAll paths are differential23The noise of LNAIn2 = 4kTegds0 1.e is the excess noise factor with respect to the basic Spice model (e=1,=2/3)2.feedback through CGD drives the Yin of the LNA away from Y*s,opt and raises the NF. HSPICE subcircuit to capture enhanced thermal noise3.The higher the CGD o

26、r the gain from gate to the drain of the input FET, the larger will be the NF2425Common-source LNA circuitcascode configuration reduce the Miller effect Complete circuit of differential common-source LNAThree downbonds LS ( 0.9 nH ) present 50 real resistance at the gate of the input MOSFETLNA2526RF

27、 mixer2.the RF mixer is 10 dB more linear than a differential pair with only one constant tail currentSIMULATION RESULTS OF ONE DIFFERENTIAL RF MIXERRF mixerIF1=188 MHz 1.Two major sources of nonlinearity in the mixer are the input transconductor and the switches2627Passive mixer with padding resist

28、ors1.The IF mixer must reject the image by 60 dB after downconversion from IF1 to IF22.Gilbert-cell-type mixers are suitable for image rejection of up to 40 dB.3. well-matched passive mixers are the better choice for higher image rejection.IF mixer 4.The Rpad is used to improve gain matching of pass

29、ive mixers27IF mixer IF mixerisolation resistors between the mixers can raise the impedance between differential inputs2828Measured on-chip image rejection for RF mixerMeasured on-chip image rejection for the IF mixerImage rejection at the first IF of more than 35 dBImage rejection at the second IF

30、of about 60 dB29296.An Excellent Gain Flatness 3.07.0 GHzCMOS PA for UWB Applicationstwo stages of amplifiers are employed in this designThe first stage consists of current-reused cascoded common-source (CS) structureL2 provide a high impedance paththe resonance circuit of L3 and C3 provide a low im

31、pedance pathThe second stage is a CS amplifier withresistive feedbackR5 and C5 are used to enhance the bandwidth and improve wider output matchingR4 helps to achieve excellent gain flatnessSchematic of the proposed 3.07.0 GHz CMOS UWB PA3030Effect of L4 on gain (post-layout simulation)If the values

32、of L4 is 0.9 nH, the flatness gain of 131.5 dB is obtained over the frequency range of interest31Measured S-parametersIt can Obtain an excellent gain flatness (S21) of 14.50.5dB over the 3.0 to 7.0 GHz frequency range .Maintain a 3 dB bandwidth of 2.8 to 7.4 GHzS11 is less than -6 dB; S22 is less th

33、an -7 dB31Measured P1dB and IIP3It can achieve A good IP1dB of -7 dBm and IIP3 of 3 dBm at 5 GHz32By adopting the current-reused technique, inter-stage inductor, and resistive feedback, the PA has excellent gain flatness about 0.5dB with smaller chip area among published works.high linearity are ach

34、ieved for the whole frequency range of interest.32COMPARISON OF UWB CMOS PA PERFORMANCES33337. Design of high-performance CMOS charge pumps in phase-locked loops1.When the PLL is used as a digital clock generator for high speed I/O interfaces, minimizing the clock skew between the internal clock and

35、 the external clock is important to get the maximum data bandwidth and the clock skew is mainly determined by the non-ideal charge pump.2.In frequency synthesis, the charge pump is the dominant block that determines the level of the unwanted FM modulation causing the reference spur. Therefore, the n

36、on-ideal effect of the charge pump should be carefully considered.343. One of the issues in the charge pump design is the leakage current which might be caused by the charge pump itself, by the on-chip varactor, or by any leakage in the board.4. The leakage current as high as 1 nA can be easily pres

37、ent in sub-micron CMOS. The phase offset due to the leakage current is usually negligible but the reference spur by the leakage current is possibly substantial in frequency synthesizers.5. Single-ended charge pumps are popular since they do not need an additional loop filter and offer low-power cons

38、umption with tri-state operation.35First one in Fig. (a) is the charge pump with the switch at the drain of the current mirror MOS. When the switch is turned off, the current pulls the drain of M1 to ground. After the switch is turned on, the voltage at the drain of M1 increases from 0V to the loop

39、filter voltage held by PLL. In the mean time, M1 has to be in the linear region till the voltage at the drain of MI is higher than the minimum saturation voltage, 1. During this time, high peak current is generated even though the charge coupling is not considered. It is caused by the voltage differ

40、ence of two series turn-on resistors from the current mirror, M1, and the switch. On the PMOS side, the same situation will occur and the matching of this peak current is difficult since the amount of the peak current varies with the output voltage. Single-ended charge pumps : (a) switch in drain, (

41、b) switch in gate, and (c) switch in source. 36Figure (b) shows the charge pump where the gate is switched instead of the drain. With this topology, the current mirrors are guaranteed to be in the saturation region. To achieve fast switching time, however, the bias current of M3 and M4 may not be sc

42、aled down since the gm3,4 affects the switching time constant in this configuration. The gate capacitance of MI and M2 is substantial when the output current of the charge pump is high and the long channel device is used for better matching. To save the constant bias current, the gated bias current

43、can be employed cooperating with the PLL at the cost of complexity .37Practical design issues in CMOS charge pumps have been discussed and several architectures are investigated.Figure 6 shows the simulation result of the differential charge pump combined with the P/FD operating at 200MHz. 388. A Wi

44、deband Variable Gain Differential CMOS LNA for Multi-standard Wireless LAN39Wideband variable gain LNAThe cascode structure with inductive degenerations is utilized in both of two stages. Such a structure can achieve a high gain, a low noise figure, and a high reverse isolation at the same time. The

45、 inductive degeneration is ideally noiseless and the input signal is pre-amplified by the input matching resonant network.the differential architecture is chosen for better rejection of on-chip interference, and it eliminates the problem of parasitic source degeneration at the same time. 1) The firs

46、t stage realizes the low noise figure; the second stage, the gain control. 2) Lg, Ls, Cex: achieve impedance matching at the input. 3) Ld, Rd: shunt-peaking components. Increase the bandwidth. 4) M5: control the feedback loop.Vcon-Vbias2Vth M5 (M5) works in the triode region with an equivalent resis

47、tance of:40. Experimental resultsS-parameter at the maximum gain(Vcon=1V)It can be observed that in the frequency range of 4.9-6 GHz the values of S11 and S22 is less than -13dB, -21dB, respectively, and the gain, S21, varies from 17.8 dB to 19.4 dB.Frequency response at different control voltage Th

48、is figure shows S21 versus the operating frequency at the different control voltages (Vcon changes from 1V to 1.8V).The results indicated that the LNA has a good wideband characteristic.41NF and NFmin at maximum gain and minimum gainThis figure shows the NF and NFmin at maximum and minimum gains. It

49、 can be seen that the NF is very close to NFmin.Gain, NF, and P1dB versus VconThis figure shows the relationship between the gain, the noise figure, and the linearity vs. Vcon at the center frequency of 5.4 GHz. It presents a large gain control range, a good linearity, even at the low gain state, th

50、e noise figure degradation is not serious.429. A wide-band active-RC filter with a fast tuning scheme for wireless communication receiversSuperiority:(1)more stable frequency response with respect to variations of components. (2)satisfies the 40dB stopband attenuation at two times the cutoff frequen

51、cy with a relatively low group delay variation.(3) The fully differential architecture could reduce the common mode noise increase the linearity characteristics at a low supply voltage.(4) The cutoff frequency and passband gain are desirably controllable with the programming codes.(5) The proper res

52、istors and capacitors are divided into the array configuration, respectively. 43Circuit DesignA. Operational amplifier B. On-chip tuning circuit using SAR schemeThe frequency characteristics of the entire filter are determined from the phase deviation from -90o at the unity-gain frequency of the eac

53、h building integrator. The phase error can be obtained asR: input resistor; C: feedback capacitor; A0: DC voltage gain; P: 3-dB pole frequency of the operational amplifier.This phase error is plotted in (a), and The fully-differential 2-stage Miller operational amplifier in (b).Fig. 3(a) shows the b

54、lock diagram of the proposed tuning circuit and Fig. 3(b) is the detailed operations.44Implementation and Experimental Results45Implementation and Experimental ResultsFig. 5(a), the cutoff frequencies are programmed to 2, 5, and 10MHz and the passband gain is also changed by the gain of the 1st ampl

55、ifier stage.Fig. 5(b) shows that the group delay variations of the filter.Fig. 6 shows the experimental result of 2-tone test .The IMD3 is measured to be 65.9dB at 5.8MHz of the output signal and the calculated IIP3 value of this filter is about 32dBm. ConclusionThe low-voltage wide-band active-RC f

56、ilter is implemented for wireless communication receivers. The 5th-order Chebyshev-II low pass filter is suitable for performing channel selection capability. The on-chip tuning circuit is proposed using the SAR scheme to promptly compensate variations of RC time constant. The filter is fabricated in a 0.18um standard digital CMOS technology and runs at a supply voltage of 1.8V.46