键盘扫描计算器VHDL仿真

1、简单计算器设计EDA实验报告一、实验内容实验要求：完成个位数的加减乘运算，输入用矩阵键盘，输出用数码管显示，每输入一次数据要显示在数码管上。矩阵键盘共16个按键，用其中10个做个位数的输入，用3个分别做加减乘运算，用其中1个做等于操作，各位数的运算结果最多两位，用动向扫描数码管显示运算结果。二、小组成员三、实现方法系统组成及连结原理以下列图，主要由由七个功能模块组成：分频模块（为键盘扫描模块和防抖模块供应时钟）、键盘扫描驱动模块（依次置零）、键盘按键值编码模块、键盘编码值防抖模块、运算模块，数码管显示驱动模块、动向扫描驱动模块。行键时值分键盘矩阵钟驱防抖频编动码数码管显运算数码管动向显示1.分

2、频模块由于FPGA实验板的原始时钟频率高达33.8688MHz，所以不能够直接接入设计模块中使用，就需要用到分频模块。将33.8688MHz分频到4KHz和10Hz来使用，一个用于行驱动扫描时钟，一个用于防抖模块。所以，采用写一个可变分频元件来调用。元件视图：主要代码以下（完满代码见附录，下同）：architectureRTLoffreq_divisioniscomponentfredivnisgeneric(n:positive);Port(clkin:inSTD_LOGIC;clkout:outSTD_LOGIC);endcomponent;beginU1:fredivngenericma

3、p(n=3)portmap(clkin=clk,clkout=clkout_kb);endRTL;仿真结果以以下列图：达到预期的目的2.行驱动模块（依次对行置零）：键盘扫描的原理就是检测行列信号尔后判断出详尽是按下了哪一个按键。所以，对行依次置零，当置零频率较快时，按下某一个按键后，必然能获取某一列的信号输出为零，以以下列图：当行信号为1110时，若按下了0键，就会获取1110的列信号，立马就快能够译码出按键值，若按下4键、8键、C键则都不会有输出。主要代码以下：process(clkin)beginifclr=1thencount=00;elsifrising_edge(clkin)then

4、ifcount=11thencount=00;elsecount=count+1;endif;endif;endprocess;process(count)beginifcount=01thenelsifcount=10thenelsifcount=11thenelsifcount=00thenendif;keydrv=1110;keydrv=1101;keydrv=1011;keydrv=0111;endprocess;仿真结果以以下列图：达到预期的目的3.键值编码模块依照行驱动模块，当按下某一个按键后，立马能够依照行列和并位信号获取唯一的键盘编码值，用5位矢量来保存结果，当没有按键按下时，

5、编码值素来保持着11111不变，并在后端的模块中不对其做任何办理。以以下出部分编码表（完满编码表见附录）：十进制数行&列HEX七段码HEX0EE7E4DE335DD5B主要代码以下：process(clk)beginifclr=0thenifrising_edge(clk)theniftemp1=11101110thenkeyvalue1=00000;-0elsiftemp1=11101101thenkeyvalue1=00001;-1elsiftemp1=11101011thenkeyvalue1=00010;-2elsiftemp1=11100111thenkeyvalue1=00011;

6、-3elsiftemp1=11011110thenkeyvalue1=00100;-4elsiftemp1=11011101thenkeyvalue1=00101;-5elsiftemp1=11011011thenkeyvalue1=00110;-6elsiftemp1=11010111thenkeyvalue1=00111;-7elsiftemp1=10111110thenkeyvalue1=01000;-8elsiftemp1=10111101thenkeyvalue1=01001;-9elsiftemp1=10111011thenkeyvalue1=01010;-10elsiftemp1

7、=10110111thenkeyvalue1=01011;-11elsiftemp1=01111110thenkeyvalue1=01100;-12elsiftemp1=01111101thenkeyvalue1=01101;-13elsiftemp1=01111011thenkeyvalue1=01110;-14elsiftemp1=01110111thenkeyvalue1test1test2test3test4test5test6test7test8test9test10test11test12test13test14test15test16null;endcase;iftest1=te

8、st5andtest2=test6andtest3=test7andtest4=test8andtest5=test9andtest6=test10andtest7=test11andtest8=test12andtest9=test13andtest10=test14andtest11=test15andtest12=test16andtest1/=UUUUUUUUthen仿真波形以下：从图中能够看出最后temp1从临时信号temp获取最后输出，达到防抖：5.运算模块当前段的模块经过防抖办理今后获取牢固的按键信号，比方1+2=3,转变成编码值就是主要代码以下：ifysfh=0thenresu

9、lt=first+second;elsifysfh=1thenresult=first-second;elsifysfh=2thenresult=first*second;endif;n=n+1;elsifn=100thenn=000;endif;endif;endprocess;process(n)beginifn=001thenkeyvaluein=conv_std_logic_vector(first,8);elsifn=011thenkeyvaluein=conv_std_logic_vector(second,8);elsifn=100thenkeyvaluein=conv_std_

10、logic_vector(result,8);endif;endprocess;仿真波形以下：以1+3=4和5x6=30为例：编码：01+03=0405X06=1E6.数码管显示模块以及动向扫描模块由于次两个模块是亲近相关的，所以一致到一起考据。经过运算获取最后的显示结果后，要在七段数码管中显示，就必定有每一个数的七段码，同时，由于前面的运算模块的结果最大能够达到81，也就是需要8位二进制，两位十进制来表示，所以就必定经过显示模块来分别出十位和个位。分别出十位和个位今后，就必定要利用动向扫描使两个数都能显示出来。由于段数码管的abcdefg位是连在一起的，只有利用分时间隔来显示，一次使能一个数

11、码管，显示一位数，当频率较高时，就可以获取两位数的显示收效。8个七数码管显示模块主要代码以下：ifnum=0thenten:=0;one:=10;elsifnum0thenten:=0;one:=num;elsifnum9thenten:=1;one:=num-10;elsifnum19thenten:=2;one:=num-20;elsifnum29thenten:=3;one:=num-30;elsifnum39thenten:=4;one:=num-40;elsifnum49thenten:=5;one:=num-50;elsifnum59thenten:=6;one:=num-60;e

12、lsifnum69thenten:=7;one:=num-70;elsifnum79thenten:=8;one:=num-80;elsifnum89thenten:=9;one:=num-90;endif;t=conv_std_logic_vector(ten,4);o=conv_std_logic_vector(one,4);动向扫描模块主要代码以下：ifcount=00thenshowout=show1;en=00000010;elsifcount=01thenshowout=show2;enshowout01100003002=showout11011016D03=showout111

13、100179由以上波形能够看出：01+02=03的计算完成了。五、总结本次EDA设计实践，完成了从VHDL代码编写到硬件实现的整个流程，掌握了一些FPGA的相关看法以及ISE软件和Active-HDL软件的使用方法。最重要的就是组员之间的合作，由于VHDL程序是模块化编写的，所以不同样模块是由不同样人来完成编译的，要达到各个模块之间能够优异的连结通信，就必定有一个很好的沟通沟通，把大家的思路集中起来，一起谈论、编写、调试程序。【附录一】完满程序：分频：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIE

14、EE.STD_LOGIC_UNSIGNED.ALL;entityfredivnisgeneric(n:integer:=3);Port(clkin:inSTD_LOGIC;clkout:outSTD_LOGIC);endfredivn;architectureBehavioraloffredivnissignalclk1:std_logic:=0;signalcounter:integerrange0ton;beginprocess(clkin)beginifrising_edge(clkin)thenifcounter=(n-1)/2thenclk1=notclk1;counter=0;el

15、secounter=counter+1;endif;endif;endprocess;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitykeyscanisPort(clr:instd_logic;clkin:inSTD_LOGIC;keydrv:outSTD_LOGIC_VECTOR(3downto0);endkeyscan;architecturebehavioralofkeyscanissignalcount:std_logic_ve

16、ctor(1downto0);beginprocess(clkin)beginifclr=1thencount=00;elsifrising_edge(clkin)thenifcount=11thencount=00;elsecount=count+1;endif;endif;endprocess;process(count)beginifcount=01thenkeydrv=1110;elsifcount=10thenkeydrv=1101;clkout=clk1;elsifcount=11thenendBehavioral;keydrv=1011;elsifcount=00thenkeyd

17、rvclkin,keydrv=keydrv1,clr=clr);tempclkin,temp=temp,key1temp1,clr=clr);key2=00001;process(clk)key3=00010;beginkey4=00011;ifclr=0thenkey5=00100;ifrising_edge(clk)thenkey6=00101;iftemp1=11101110key7=00110;thenkeyvalue1=00000;key8=00111;elsiftemp1=11101101thencount1=000;keyvalue1=00001;start_1=1;elsift

18、emp1=11101011elsethenkeyvalue1=00010;ifrising_edge(clk_f)thenelsiftemp1=11100111ifcount1=111thenthenkeyvalue1=00011;count1=000;elsiftemp1=11011110elsecount1=count1+1;thenkeyvalue1=00100;endif;elsiftemp1=11011101endif;thenkeyvalue1=00101;endif;elsiftemp1=11011011casecount1isthenkeyvalue1key1key2=keyc

19、ode;thenkeyvalue1key3key4=keycode;thenkeyvalue1key5key6=keycode;thenkeyvalue1key7key8=keycode;thenkeyvalue1null;elsiftemp1=10110111endcase;thenkeyvalue1=01011;ifkey1=key2andkey2=key3andelsiftemp1=01111110key3=key4andkey4=key5andthenkeyvalue1=01100;key5=key6andkey6=key7andelsiftemp1=01111101key7=key8

20、andkey1/=UUUUUthenthenkeyvalue1=01101;elsiftemp1=01111011keycode1=key1;start_1=0thenkeyvalue1=01110;after5ns;elsiftemp1=01110111endif;thenkeyvalue1=01111;endprocess;endif;start=start_1;endif;endfangdou;endif;endprocess;keycode=keyvalue1;endrtl;运算：数码管显示：libraryIEEE;libraryIEEE;useIEEE.STD_LOGIC_1164.

21、ALL;useIEEE.STD_LOGIC_1164.all;useIEEE.STD_LOGIC_ARITH.ALL;useieee.std_logic_arith.all;useIEEE.STD_LOGIC_UNSIGNED.ALL;useieee.std_logic_unsigned.all;useieee.numeric_std.all;entityshumaguanxianshiisentityyunsuanisport(keyvaluein:inport(start:instd_logic;std_logic_vector(7downto0);keycode1:instd_logic

22、_vector(4downto0);clk:instd_logic;keyvaluein:outstd_logic_vector(7downto0);show1,show2:outendyunsuan;std_logic_vector(6downto0);architectureBehavioralofyunsuanisendshumaguanxianshi;signalfirst,second,result,ysfh:integerarchitectureshumaguanxianshirange0to99;ofshumaguanxianshiissignaln:std_logic_vect

23、or(2downto0);signalt:std_logic_vector(3begindownto0);process(start,keycode1)signalo:std_logic_vector(3begindownto0);ifstart=1thenbeginn=000;process(clk)elseifn=000thenvariablenum:integerrange0to99;ifkeycode1=00001thenfirst=1;variableten,one:integerrange0toelsifkeycode1=00010then15;first=2;beginelsif

24、keycode1=00011thenfirst=3;ifrising_edge(clk)thenelsifkeycode1=00100thenfirst=4;num:=conv_integer(keyvaluein);elsifkeycode1=00101thenfirst=5;ifnum=0thenelsifkeycode1=00110thenfirst=6;elsifkeycode1=00111thenfirst=7;elsifkeycode1=01000thenfirst=8;elsifkeycode1=01001thenfirst=9;elsifkeycode1=00000thenfi

25、rst=0;endif;n=n+1;elsifn=001thenifkeycode1=01010thenysfh=0;elsifkeycode1=01011thenysfh=1;elsifkeycode1=01100thenysfh=2;endif;n=n+1;elsifn=010thenifkeycode1=00001thensecond=1;elsifkeycode1=00010thensecond=2;elsifkeycode1=00011thensecond=3;elsifkeycode1=00100thensecond=4;elsifkeycode1=00101thensecond=

26、5;elsifkeycode1=00110thensecond=6;elsifkeycode1=00111thensecond=7;elsifkeycode1=01000thensecond=8;elsifkeycode1=01001thensecond=9;elsifkeycode1=00000thensecond=0;endif;n=n+1;elsifn=011andkeycode1=01101thenifysfh=0thenresult=first+second;elsifysfh=1thenresult=first-second;elsifysfh=2thenresult=first*

27、second;endif;n=n+1;elsifn=100thenn=000;endif;endif;endprocess;process(n)beginifn=001thenkeyvaluein=conv_std_logic_vector(first,8);elsifn=011thenkeyvaluein=conv_std_logic_vector(second,8);elsifn=100thenkeyvaluein=conv_std_logic_vector(result,8);ten:=0;one:=10;elsifnum0thenten:=0;one:=num;elsifnum9the

28、nten:=1;one:=num-10;elsifnum19thenten:=2;one:=num-20;elsifnum29thenten:=3;one:=num-30;elsifnum39thenten:=4;one:=num-40;elsifnum49thenten:=5;one:=num-50;elsifnum59thenten:=6;one:=num-60;elsifnum69thenten:=7;one:=num-70;elsifnum79thenten:=8;one:=num-80;elsifnum89thenten:=9;one:=num-90;endif;t=conv_std

29、_logic_vector(ten,4);oshow1show1show1show1show1show1show1show1show1show1show1show2show2show2show2show2show2show2show2show2show2show2=0000000;endcase;endif;endprocess;endshumaguanxianshi;动向显示：键盘：libraryIEEE;libraryIEEE;useuseIEEE.STD_LOGIC_1164.ALL;IEEE.STD_LOGIC_1164.all;useIEEE.STD_LOGIC_ARITH.ALL;

30、useuseIEEE.STD_LOGIC_UNSIGNED.ALL;IEEE.STD_LOGIC_UNSIGNED.entitykeyboardisALL;Port(clr:instd_logic;useclk:inSTD_LOGIC;ieee.numeric_std.all;keyin:inSTD_LOGIC_VECTOR(3downto0);entityshaomiaoxianshikeydrv1:outstd_logic_vector(3downto0);iskeyvalue:outSTD_LOGIC_VECTOR(4downto0);port(clk,clr:instd_logic;s

31、tart:outstd_logic);show1:inendkeyboard;std_logic_vector(6downtoarchitectureRTLofkeyboardis0);componentkeyscanshow2:inPort(clkin,clr:inSTD_LOGIC;std_logic_vector(6downtokeydrv:outSTD_LOGIC_VECTOR(3downto0);0);endcomponent;showout:outcomponentkeydecoderstd_logic_vector(6downtoPort(clkin,clk,clr:instd_

32、logic;0);keyin:inSTD_LOGIC_VECTOR(3downto0);en:outkeycode:outSTD_LOGIC_VECTOR(4downtostd_logic_vector(7downto0);0);endcomponent;endshaomiaoxianshi;componentfangdouarchitectureport(keycode:instd_logic_vector(4downto0);shaomiaoxianshiofkeycode1:outstd_logic_vector(4downto0);shaomiaoxianshiisstart:outstd_logic;signalclk_f,clr:instd_logic);count:std_logic_vector(1endcomponent;downto0);componentfredivnbegingeneric(n:integer:=3);process(clk)Port(clkin:inSTD_LOGIC;beginclkout:outSTD_LOGIC);ifclr=1thencount=00;elseifclkeventandclk=1thenifcount=01thencount=00;elsec