毕业论文：89c51单片机英语文献翻译

毕业论文：89c51单片机英语文献翻译19有关AT89C51的介绍英文原文DescriptionTheAT89C51isalow-powerhigh-performanceCMOS8-bitmicrocomputerwith4KbytesofFlashProgrammableandErasableReadOnlyMemoryPEROMand128bytesRAMThedeviceismanufacturedusingAtmelshighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandardMCS-51instructionsetandpinoutThechipcombinesaversatile8-bitCPUwithFlashonamonolithicchiptheAtmelAT89C51isapowerfulmicrocomputerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplicationsFeaturesCompatiblewithMCS-51Products4KBytesofIn-SystemReprogrammableFlashMemoryEndurance1000WriteEraseCyclesFullyStaticOperation0Hzto24MHzThree-LevelProgramMemoryLock128x8-BitInternalRAM32ProgrammableIOLinesTwo16-BitTimerCountersSixInterruptSourcesProgrammableSerialChannelLowPowerIdleandPowerDownModesTheAT89C51providesthefollowingstandardfeatures4KbytesofFlash128bytesofRAM32IOlinestwo16-bittimercountersafivevectortwo-levelinterruptarchitectureafullduplexserialporton-chiposcillatorandclockcircuitryInadditiontheAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodesTheIdleModestopstheCPUwhileallowingtheRAMtimercountersserialportandinterruptsystemtocontinuefunctioningThePowerDownModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwareresetBlockDiagramPinDescriptionVCCSupplyvoltageGNDGroundPort0Port0isan8-bitopendrainbidirectionalIOportAsanoutputporteachpincansinkeightTTLinputsWhenisarewrittentoport0pinsthepinscanbeusedashighimpedanceinputsPort0mayalsobeconfiguredtobethemultiplexedloworderaddressdatabusduringaccessestoexternalprogramanddatamemoryInthismodeP0hasinternalpullupsPort0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverificationExternalpullupsarerequiredduringprogramverificationPort1Port1isan8-bitbidirectionalIOportwithinternalpullupsThePort1outputbufferscansinksourcefourTTLinputsWhen1sarewrittentoPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputsAsinputsPort1pinsthatareexternallybeingpulledlowwillsourcecurrentIILbecauseoftheinternalpullupsPort1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverificationPort2Port2isan8-bitbidirectionalIOportwithinternalpullupsThePort2outputbufferscansinksourcefourTTLinputsWhen1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputsAsinputsPort2pinsthatareexternallybeingpulledlowwillsourcecurrentIILbecauseoftheinternalpullupsPort2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddressesMOVXDPTRInthisapplicationitusesstronginternalpull-upswhenemitting1sDuringaccessestoexternaldatamemorythatuse8-bitaddressesMOVXRIPort2emitsthecontentsoftheP2SpecialFunctionRegisterPort2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverificationPort3Port3isan8-bitbidirectionalIOportwithinternalpullupsThePort3outputbufferscansinksourcefourTTLinputsWhen1sarewrittentoPort3pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputsAsinputsPort3pinsthatareexternallybeingpulledlowwillsourcecurrentIILbecauseofthepullupsPort3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelowPortpin alternatefunctions P30 rxdserialinputport P31 txdserialoutputport P32 int0externalinterrupt0 P33 int1externalinterrupt1 P34 t0timer0externalinput P35 t1timer1externalinput P36 WRexternaldatamemorywritestrobe P37 rdexternaldatamemoryreadstrobe Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverificationRSTResetinputAhighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedeviceALEPROGAddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemoryThispinisalsotheprogrampulseinputPROGduringFlashprogrammingInnormaloperationALEisemittedataconstantrateof16theoscillatorfrequencyandmaybeusedforexternaltimingorclockingpurposesNotehoweverthatoneALEpulseisskippedduringeachaccesstoexternalDataMemoryIfdesiredALEoperationcanbedisabledbysettingbit0ofSFRlocation8EHWiththebitsetALEisactiveonlyduringaMOVXorMOVCinstructionOtherwisethepinisweaklypulledhighSettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmodePSENProgramStoreEnableisthereadstrobetoexternalprogrammemoryWhentheAT89C51isexecutingcodefromexternalprogrammemoryPSENisactivatedtwiceeachmachinecycleexceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemoryEAVPPExternalAccessEnableEAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFHNotehoweverthatiflockbit1isprogrammedEAwillbeinternallylatchedonresetEAshouldbestrappedtoVCCforinternalprogramexecutionsThispinalsoreceivesthe12-voltprogrammingenablevoltageVPPduringFlashprogrammingforpartsthatrequire12-voltVPPXTAL1InputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuitXTAL2OutputfromtheinvertingoscillatoramplifierOscillatorCharacteristicsXTAL1andXTAL2aretheinputandoutputrespectivelyofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillatorasshowninFigure1EitheraquartzcrystalorceramicresonatormaybeusedTodrivethedevicefromanexternalclocksourceXTAL2shouldbeleftunconnectedwhileXTAL1isdrivenasshowninFigure2Therearenorequirementsonthedutycycleoftheexternalclocksignalsincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flopbutminimumandimumvoltagehighandlowtimespecificationsmustbeobservedIdleModeInidlemodetheCPUputsitselftosleepwhilealltheonchipperipheralsremainactiveThemodeisinvokedbysoftwareThecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismodeTheidlemodecanbeterminatedbyanyenabledinterruptorbyahardwareresetItshouldbenotedthatwhenidleisterminatedbyahardwareresetthedevicenormallyresumesprogramexecutionfromwhereitleftoffuptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrolOn-chiphardwareinhibitsaccesstointernalRAMinthiseventbutaccesstotheportpinsisnotinhibitedToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyresettheinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemoryStatusofExternalPinsDuringIdleandPowerDownModesmode Programmemory ALE psen Port0 Port1 Port2 Port3 idle internal 1 1 data data data Data Idle External 1 1 float Data data Data Powerdown Internal 0 0 Data Data Data Data Powerdown External 0 0 float data Data data PowerDownModeInthepowerdownmodetheoscillatorisstoppedandtheinstructionthatinvokespowerdownisthelastinstructionexecutedTheon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepowerdownmodeisterminatedTheonlyexitfrompowerdownisahardwareresetResetredefinestheSFRsbutdoesnotchangetheon-chipRAMTheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilizeProgramMemoryLockBitsOnthechiparethreelockbitswhichcanbeleftunprogrammedUorcanbeprogrammedPtoobtaintheadditionalfeatureslistedinthetablebelowLockBitProtectionModesProgramlockbits Protectiontype Lb1 Lb2 Lb3 1 U U U Noprogramlockfeatures 2 P U U Movcinstructionsexecutedfromexternalprogrammemoryaredisablefromfetchingcodebytesfrominternalmemoryeaissampledandlatchedonresetandfurtherprogrammingoftheflashdisabled 3 P P U Sameasmode2alsoverifyisdisable 4 P P P Sameasmode3alsoexternalexecutionisdisabled Whenlockbit1isprogrammedthelogiclevelattheEApinissampledandlatchedduringresetIfthedeviceispoweredupwithoutaresetthelatchinitializestoarandomvalueandholdsthatvalueuntilresetisactivatedItisnecessarythatthelatchedvalueofEAbeinagreementwiththecurrentlogiclevelatthatpininorderforthedevicetofunctionproperlyProgrammingtheFlashTheAT89C51isnormallyshippedwiththeon-chipFlashmemoryarrayintheerasedstatethatiscontentsFFHandreadytobeprogrammedTheprogramminginterfaceacceptseitherahigh-voltage12-voltoralow-voltageVCCprogramenablesignalThelowvoltageprogrammingmodeprovidesaconvenientwaytoprogramtheAT89C51insidetheuserssystemwhilethehigh-voltageprogrammingmodeiscompatiblewithconventionalthirdpartyFlashorEPROMprogrammersTheAT89C51isshippedwitheitherthehigh-voltageorlow-voltageprogrammingmodeenabledTherespectivetop-sidemarkinganddevicesignaturecodesarelistedinthefollowingtable Vpp12v Vpp5v Top-sidemark AT89C51xxxxyyww AT89C51xxxx-5yyww signature 030H1EH031H51H032HFFH 030H1EH031H51H032H05H TheAT89C51codememoryarrayisprogrammedbyte-bybyteineitherprogrammingmodeToprogramanynonblankbyteintheon-chipFlashProgrammableandErasableReadOnlyMemorytheentirememorymustbeerasedusingtheChipEraseModeProgrammingAlgorithmBeforeprogrammingtheAT89C51theaddressdataandcontrolsignalsshouldbesetupaccordingtotheFlashprogrammingmodetableandFigures3and4ToprogramtheAT89C51takethefollowingsteps1Inputthedesiredmemorylocationontheaddresslines2Inputtheappropriatedatabyteonthedatalines3Activatethecorrectcombinationofcontrolsignals4RaiseEAVPPto12Vforthehigh-voltageprogrammingmode5PulseALEPROGoncetoprogramabyteintheFlasharrayorthelockbitsThebyte-writecycleisself-timedandtypicallytakesnomorethan15msRepeatsteps1through5changingtheaddressanddatafortheentirearrayoruntiltheendoftheobjectfileisreachedDataPollingTheAT89C51featuresDataPollingtoindicatetheendofawritecycleDuringawritecycleanattemptedreadofthelastbytewrittenwillresultinthecomplementofthewrittendatumonPO7OncethewritecyclehasbeencompletedtruedataarevalidonalloutputsandthenextcyclemaybeginDataPollingmaybeginanytimeafterawritecyclehasbeeninitiatedReadyBusyTheprogressofbyteprogrammingcanalsobemonitoredbytheRDYBSYoutputsignalP34ispulledlowafterALEgoeshighduringprogrammingtoindicateBUSYP34ispulledhighagainwhenprogrammingisdonetoindicateREADYProgramVerifyIflockbitsLB1andLB2havenotbeenprogrammedtheprogrammedcodedatacanbereadbackviatheaddressanddatalinesforverificationThelockbitscannotbeverifieddirectlyVerificationofthelockbitsisachievedbyobservingthattheirfeaturesareenabledChipEraseTheentireFlashProgrammableandErasableReadOnlyMemoryarrayiserasedelectricallybyusingthepropercombinationofcontrolsignalsandbyholdingALEPROGlowfor10msThecodearrayiswrittenwithall1sThechiperaseoperationmustbeexecutedbeforethecodememorycanbere-programmedReadingtheSignatureBytesThesignaturebytesarereadbythesameprocedureasanormalverificationoflocations030H031Hand032HexceptthatP36andP37mustbepulledtoalogiclowThevaluesreturnedareasfollows030H1EHindicatesmanufacturedbyAtmel031H51Hindicates89C51032HFFHindicates12Vprogramming032H05Hindicates5VprogrammingProgrammingInterfaceEverycodebyteintheFlasharraycanbewrittenandtheentirearraycanbeerasedbyusingtheappropriatecombinationofcontrolsignalsThewriteoperationcycleisselftimedandonceinitiatedwillautomaticallytimeitselftocompletionTable1FlashProgrammingModes mode RST PSEN ALEPROG EAVpp P26 P27 P36 P37 Writecodedata H L H12V L H H H Readcodedata H L H H L L H H Writelock Bit-1 H L H12V H H H H Bit-2 H L H12V H H L L Bit-3 H L H12V H L H L Chiperase H L H12V H L L L Readsignaturesyte H L H H L L L L Note1chiperaserequiresa10-msPROGpulseFigure3ProgrammingtheFlashFigure4VerifyingtheFlashFlashProgrammingandVerificationCharacteristicsTA0°Cto70°CVCC5010Symbol parameter min Units Vpp⑴ Programmingenablevoltage 115 125 V Ipp⑴ Programmingenablecurrent 10 mA 1Tclcl Oscillatorfrequency 3 24 MHZ Tavgl AddresssetuptoPSENlow 48Tclcl Tghax AddressholeafterPSEN 48Tclcl Tdvgl DatasetuptoPSENlow 48Tclcl Tghdx DataholeafterPSEN 48Tclcl Tehsh P27enablehightoVpp 48Tclcl Tshgl VppsetuptoPSENlow 10 us Tghsl⑴ VppholeafterPSEN 10 us Tglgh PSENwidth 1 110 us Tavqv Addresstodatavalid 48Tclcl Telqv enablelowtodatavalid 48Tclcl Tehqz Datafloatafterenable 0 48Tclcl Tghbl PSENhightobusylow 10 us Twc Bytewritecycletime 20 ms Note1Onlyusedin12-voltprogrammingmodeFlashProgrammingandVerificationWaveforms-HighVoltageModeVPP12VFlashProgrammingandVerificationWaveforms-LowVoltageModeVPP5VAbsoluteimumRatingsOperatingTemperature-55°Cto125°CStorageTemperature-65°Cto150°CVoltageonAnyPinwithRespecttoGround-10Vto70VimumOperatingVoltage66VDCOutputCurrent150mADCCharacteristicsTA-40°Cto85°CVCC50V20unlessotherwisenotedsymbol parameter condition min units Vil Inputlowvoltage exceptEA -05 02Vcc-01 V Vil1 InputlowvoltageEA -05 02Vcc-03 V Vih Inputhighvoltage ExceptXTAL1XTAL2 02Vcc09 Vcc05 V Vih1 Inputhighvoltage XTAL1RST 07Vcc Vcc05 V Vol Outputlowvoltage⑴ports123 Iol16mA 045 V Vol1 Outputlowvoltage⑴port0ALEPSEN Ioh32mA 045 V Ioh-60uAVcc-5V10 24 Ioh-25uA 075Vcc Voh Outputhighvoltage⑴ports123 Ioh-60uAVcc5V10 09Vcc V Voh1 Outputlowvoltage⑴port0ALEPSEN Ioh-800UAVcc5V10 24 V Ioh-300uA 075Vcc V Ioh-80uA 09Vcc V Iil Logical0inputcurrentports123 Vin045V -50 uA Itl Logical1to0transitioncurrentports123 Vin2VVcc5V10 -650 uA Ili Inputleakagecurrentport0EA 045VinVcc 50 10 uA RRST Resetpulldownresistor 300 kom Cio Pincapacitance Testfreq1MHZTA25℃ 10 pF Icc Powersupplycurrent Activemode12MHZ 20 mA Idlemode12MHZ 5 mA Powerdownmode⑵ Vcc6V 100 uA Vcc3V 40 uA Notes1Understeadystatenon-transientconditionsIOLmustbeexternallylimitedasfollowsimumIOLperportpin10mAimumIOLper8-bitportPort026mAPorts12315mAimumtotalIOLforalloutputpins71mA2MinimumVCCforPowerDownis2VACCharacteristicsUnderOperatingConditionsLoadCapacitanceforPort0ALEPROGandPSEN100pFLoadCapacitanceforallotheroutputs80pFExternalProgramandDataMemoryCharacteristicsSymbol Parameter 12MHzOscillator 16to24MHzOscillator Units Min Min 1TCLCL OscillatorFrequency 0 24 MHz TLHLL ALEPulseWidth 127 2TCLCL-40 ns TAVLL AddressValidtoALELow 43 TCLCL-13 ns TLLAX AddressHoldAfterALELow 48 TCLCL-20 ns TLLIV ALELowtoValidInstructionIn 233 4TCLCL-65 ns TLLPL ALELowtoPSENLow 43 TCLCL-13 ns TPLPH PSENPulseWidth 205 3TCLCL-20 ns TPLIV PSENLowtoValidInstructionIn 145 3TCLCL-45 ns TPXIX InputInstructionHoldAfterPSEN 0 0 ns TPXIZ InputInstructionFloatAfterPSEN 59 TCLCL-10 ns TPXAV PSENtoAddressValid 75 TCLCL-8 ns TAVIV AddresstoValidInstructionIn 312 5TCLCL-55 ns TPLAZ PSENLowtoAddressFloat 10 10 ns TRLRH RDPulseWidth 400 6TCLCL-100 ns TWLWH WRPulseWidth 400 6TCLCL-100 ns TRLDV RDLowtoValidDataIn 252 5TCLCL-90 ns TRHDX DataHoldAfterRD 0 0 ns TRHDZ DataFloatAfterRD 97 2TCLCL-28 ns TLLDV ALELowtoValidDataIn 517 8TCLCL-150 ns TAVDV AddresstoValidDataIn 585 9TCLCL-165 ns TLLWL ALELowtoRDorWRLow 200 300 3TCLCL-50 3TCLCL50 ns TAVWL AddresstoRDorWRLow 203 4TCLCL-75 ns TQVWX DataValidtoWRTransition 23 TCLCL-20 ns TQVWH DataValidtoWRHigh 433 7TCLCL-120 ns TWHQX DataHoldAfterWR 33 TCLCL-20 ns TRLAZ RDLowtoAddressFloat 0 0 ns TWHLH RDorWRHightoALEHigh 43 123 TCLCL-20 TCLCL25 ns ExternalProgramMemoryReadCycleExternalDataMemoryReadCycleExternalDataMemoryWriteCycleExternalClockDriveWaveformsExternalClockDrive符号 参数 最小值 最大值 单位 1TCLCL OscillatorFrequency 0 24 MHz TCLCL ClockPeriod 416 ns TCHCX HighTime 15 ns TCLCX LowTime 15 ns TCLCH RiseTime 20 ns TCHCL FallTime 20 ns SerialPortTimingShiftRegisterModeTestConditionsVCC50V20LoadCapacitance80pF符号 参数 12MHzOsc VariableOscillator Units Min Min TXLXL SerialPortClockCycleTime期 10 12TCLCL us TQVXH OutputDataSetuptoClockRisingEdge 700 10TCLCL-133 ns TXHQX OutputDataHoldAfterClockRisingEdge 50 2TCLCL-117 ns TXHDX InputDataHoldAfterClockRisingEdge 0 0 ns TXHDV ClockRisingEdgetoInputDataValid 700 10TCLCL-133 ns ShiftRegisterModeTimingWaveformsACTestingInputOutputWaveforms1Note1ACInputsduringtestingaredrivenatVCC-05Vforalogic1and045Vforalogic0TimingmeasurementsaremadeatVIHminforalogic1andVILforalogic0FloatWaveforms1Note1Fortimingpurposesaportpinisnolongerfloatingwhena100mVchangefromloadvoltageoccursAportpinbeginstofloatwhen100mVchangefromtheloadedVOHVOLleveloccursOrderingInformationSpeedMHz PowerSupply OrderingCode Package OperationRange 12 5V20 AT89C51-12ACAT89C51-12JCAT89C51-12PCAT89C51-12QC 44A44J40P644Q Commercial0Cto70C AT89C51-12AIAT89C51-12JIAT89C51-12PIAT89C51-12QI 44A44J40P644Q Industrial-40Cto85C 16 5V20 AT89C51-16ACAT89C51-16JCAT89C51-16PCAT89C51-16QC 44A44J40P644Q Commercial0Cto70C AT89C51-16AIAT89C51-16JIAT89C51-16PIAT89C51-16QI 44A44J40P644Q Industrial-40Cto85C 20 5V20 AT89C51-20ACAT89C51-20JCAT89C51-20PCAT89C51-20QC 44A44J40P644Q Commercial0Cto70C AT89C51-20AIAT89C51-20JIAT89C51-20PIAT89C51-20QI 44A44J40P644Q Industrial-40Cto85C 24 5V20 AT89C51-24ACAT89C51-24JCAT89C51-24PCAT89C51-24QC 44A44J40P644Q Commercial0Cto70C AT89C51-24AIAT89C51-24JIAT89C51-24PIAT89C51-24QI 44A44J40P644Q Industrial-40Cto85C PackageType 44A 44LeadThinPlasticGullWingQuadFlatpackTQFP 44J 44LeadPlasticJ-LeadedChipCarrierPLCC 40P6 40Lead0600WidePlasticDualInlinePackagePDIP 44Q 44LeadPlasticGullWingQuadFlatpackPQFP P89C51SpecialFunctionRegistersSYMBOL DESCRIPTION BYTESADDRESS BITADDRESSSYMBOL ACC Accumulator E0H E7E6E5E4E3E2E1E0ACC7ACC6ACC5ACC4ACC3ACC2ACC1ACC0 B Bregister F0H F7F6F5F4F3F2F1F0B7B6B5B4B3B2B1B0 DPH DataPointerHigh 83H DPL DataPointerLow 82H IE InterruptEnable A8H AF–-–-ACABAAA9A8EAESET1EX1ET0EX0 IP InterruptPriority B8H –-–-–-BCBBBAB9B8–-–-–-PSPT1PX1PT0PX0 P0 Port0 80H 8786858483828180P07P06P05P04P03P02P01P00 P1 Port1 90H 9796959493929190P17P16P15P14P13P12P11P10 P2 Port2 A0H A7A6A5A4A3A2A1A0P27P26P25P24P23P22P21P20 P3 Port3 B0H B7B6B5B4B3B2B1B0P37P36P35P34P33P32P31P30 PCON PowerControl 87H 8D–-–-–-–-–-–-–-SMOD PSW ProgramStatusWord D0H D7D6D5D4D3D2D1D0CYACF0RS1RS0OV–-P SBUF SerialDataBuffer 99H SCON SerialControl 98H 9F9E9D9C9B9A9998SM0SM1SM2RENTB8RB8TIRI SP StackPointer 81H TCON TimerControlControl 88H 8F8E8D8C8B8A8988TF1TR1TF0TR0IE1IT1IE0IT0 TH0 TimerHigh0 8CH TH1 TimerHigh1 8DH TL0 TimerLow0 8AH TL1 TimerLow1 8BH TMOD TimerMode 89H GATECTM1M0GATECTM1M0 SFRsarebitaddressable–ReservedbitsResetvaluedependsonresetsource有关AT89C51的介绍描述AT89C51是美国ATMEL公司生产的低电压高性能CMOS8位单片机片内含4Kbytes的快速可擦写的只读程序存储器PEROM和128bytes的随机存取数据存储器RAM器件采用ATMEL公司的高密度非易失性存储技术生产兼容标准MCS-51产品指令系统片内置通用8位中央处理器CPU和flish存储单元功能强大AT89C51单片机可为您提供许多高性价比的应用场合可灵活应用于各种控制领域主要性能参数与MCS-51产品指令系统完全兼容4K字节可重复写flash闪速存储器1000次擦写周期全静态操作0HZ－24MHZ三级加密程序存储器1288字节内部RAM32个可编程IO口2个16位定时／计数器6个中断源可编程串行UART通道低功耗空闲和掉电模式功能特性概述AT89C51提供以下标准功能4K字节flish闪速存储器128字节内部RAM32个IO口线两个16位定时／计数器一个5向量两级中断结构一个全双工串行通信口片内振荡器及时钟电路同时AT89C51可降至0HZ的静态逻辑操作并支持两种软件可选的节电工作模式空闲方式停止CPU的工作但允许RAM定时／计数器串行通信口及中断系统继续工作掉电方式保存RAM中的内容但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位方框图引脚功能说明Vcc电源电压GND地P0口P0口是一组8位漏极开路型双向IO口也即地址数据总线复位口作为输出口用时每位能吸收电流的方式驱动8个逻辑门电路对端口写1可作为高阻抗输入端用在访问外部数据存储器或程序存储器时这组口线分时转换地址低8位和数据总线复用在访问期间激活内部上拉电阻P1口P1是一个带内部上拉电阻的8位双向IO口P1的输出缓冲级可驱动吸收或输出电流4个TTL逻辑门电路对端口写1通过内部的上拉电阻把端口拉到高电平此时可做熟出口做输出口使用时因为内部存在上拉电阻某个引脚被外部信号拉低时会输出一个电流IilFlash编程和程序校验期间P1接受低8位地址P2口P2是一个带有内部上拉电阻的8位双向IO口P2的输出缓冲级可驱动吸收或输出电流4个TTL逻辑门电路对端口写1通过内部地山拉电阻把端口拉到高电平此时可作为输出口作输出口使用时因为内部存在上拉电阻某个引脚被外部信号拉低时会输出一个电流Iil在访问外部程序存储器获16位地址的外部数据存储器例如执行MOVXDPTR指令时P2口送出高8位地址数据在访问8位地址的外部数据存储器如执行MOVXRI指令时P2口线上的内容也即特殊功能寄存器SFR区中R2寄存器的内容在整个访问期间不改变Flash编程或校验时P2亦接受高地址和其它控制信号P3口P3口是一组带有内部上拉电阻的8位双向IO口P3口输出缓冲级可驱动吸收或输出电流4个TTL逻辑门电路对P3口写入1时他们被内部上拉电阻拉高并可作为输出口做输出端时被外部拉低的P3口将用上拉电阻输出电流IilP3口除了作为一般的IO口线外更重要的用途是它的第二功能如下表所示端口引脚 第二功能 P30 rxd串行输入口 P31 txd串行输出口 P32 int0外中断0 P33 int1外中断1 P34 t0定时计数器0 P35 t1定时计数器1 P36 WR外部数据存储器写选通 P37 RD外部数据存储器读选通 P3口还接收一些用于flash闪速存储器编程和程序校验的控制信号RST复位输入当振荡器工作时RST引脚出现两个机器周期以上高电平将使单片机复位ALEPROG当访问外部程序存储器或数据存储器时ALE地址所存允许输出脉冲用于所存地址的低8位字节即使不访问外部存储器ALE仍以时钟振荡频率的16输出固定的正脉冲信号因此它可对外输出时钟或用于定时目的要注意的是每当访问外部数据存储器时将跳过一个ALE脉冲对flash存储器编程期间该引脚还用于输入编程脉冲PROG如有不要可通过对特殊功能寄存器SFR区中的8EH单元的D0位置位可禁止ALE操作该外置位后只要一条MOVX和MOVC指令ALE才会被激活此外该引脚会被微弱拉高单片机执行外部程序时应设置ALE无效PSEN程序存储允许PSEN输出是外部程序存储器的读选通信号当AT89C51由外部程序存储器取指令或数据时每个机器周期两个PSEN有效即输出两个脉冲在此期间当访问外部数据存储器这两次有效的PSEN信号不出现EAVPP外部访问允许欲使CPU仅访问外部程序存储器地址为0000H---FFFFHEA端必须保持低电平接地需注意的是如果加密位LB1被编程复位时内部会锁存EA端状态如EA端为高电平接VCC端CPU则执行内部程序存储器中的指令Flash存储器编程时该引脚加上12V的编程允许电源VPP当然这必须是该器件是使用12V编程电压VPPXTAL1振荡器反相放大器的及内部时钟发生器的输出端XTAL2振荡器反相放大器的输出端时钟振荡器AT89C51中有一个用于构成内部振荡器的高增益反相放大器引脚XTAL1和XTAL2分别是该放大器的输入端和输出端这个放大器与作为反馈的片外石英晶体或陶瓷谐振器一起构成自激振荡器振荡电路参见图5外接石英晶体或陶瓷谐振器及电容C1C2接在放大器的反馈回路中构成并联振荡电路对外接电容C1C2虽然没有十分严格的要求但电容容量的大小会轻微影响振荡频率的高低振荡器的稳定性起振的难易程度及温度稳定性如果使用石英晶体我们推荐电容使用30PF10PF而如使用陶瓷谐振器建议选择40PF10PF用户也可以采用外部时钟采用外部时钟的电路如图5右所示这种情况下外部时钟脉冲接到XTAL1端即内部时钟发生器的输入端XTAL2则悬空由于外部时钟信号是通过一个2分频触发器后作为内部时钟信号的所以对外部时钟信号的占空比没有特殊要求但最小高电平持续时间和最大的低电平持续时间应符合产品技术要求空闲模式在空闲工作模式状态CPU保持睡眠状态而所有片内的外设仍保持激活状态这种方式由软件产生此时片内RAM和所有特殊功能寄存器的内容保持不变空闲模式可由任何允许的中断请求或硬件复位终止终止空闲工作模式的方法有两种其一是任何一条被允许中断的事件被激活即可终止空闲工作模式程序会首先响应中断进入中断服务程序执行完中断服务程序并仅随终端返回指令下一条要执行的指令就是使单片机进入空闲模式那条指令后面的一条指令其二是通过硬件复位也可将空闲工作模式终止需要注意的是当由硬件复位来终止空闲模式时CPU通常是从激活空闲模式那条指令的下一条指令开始继续执行程序的要完成内部复位操作硬件复位脉冲要保持两个机器周期24个时钟周期有效在这种情况下内部禁止CPU访问片内RAM而允许访问其它端口为了避免可能对端口产生以外写入激活空闲模式的那条指令后一条指令不应该是一条对端口或外部存储器的写入指令空闲和掉电模式外部引脚状态模式 程序存储器 ALE PSEN PORT0 PORT1 PORT2 PORT3 空闲模式 内部 1 1 数据 数据 数据 数据 空闲模式 外部 1 1 浮空 数据 数据 数据 掉电模式 内部 0 0 数据 数据 数据 数据 掉电模式 外部 0 0 浮空 数据 数据 数据 掉电模式在掉电模式下震荡器停止工作进入掉电模式的指令是最后一条被执行的指令片内RAM和特殊功能寄存器的内容在终止掉电模式前被冻结退出掉电模式的唯一方法是硬件复位复位后将重新定义全部特殊功能寄存器但不改变RAM中的内容在VCC恢复到正常工作电平前复位应无效且必须保持一定时间以使振荡器重启动并稳定工作程序存储器的加密AT89C51可使用对芯片上的3个加密位进行编程P或不编程U来得到如下表所示的功能加密位保护功能表程序加密位 保护类型 LB1 LB2 LB3 1 U U U 没有程序保护功能 2 P U U 禁止从外部程序存储器中执行MOVC指令读取内部程序存储器的内容 3 P P U 除上表功能外还禁止程序校验 4 P P P 除以上功能外同时禁止外部执行 当加密位LB1被编程时在复位期间EA端的逻辑电平被采样并锁存如果单片机上电后一直没有复位则锁存起的初始值是一个随机数且这个随机数会一直保持到真正复位为止为使单片机能正常工作被锁存的EA电平值必须与该引脚当前的逻辑电平一致此外加密位只能通过整片擦除的方法清除FLASH闪速存储器的编程AT89C51单片机内部有4K字节的FLASHPEROM这个FLASH存储阵列出厂时已处于擦除状态即所有存储单元的内容均为FFH用户随时可对其进行编程编程接口可接收高电平12V或低电平VCC的允许编程信号低电平编程模式适合于用户再线编程系统而高电平编程模式可与通用EPROM编程器兼容AT89C51单片机中有些属于低电压编程方式而有些则是高电平编程方式用户可从芯片上的型号和读取芯片内的签名字节获得该信息见下表 Vpp12v Vpp5v 芯片顶面标识 AT89C51xxxxyyww AT89C51xxxx-5yyww 签名字节 030H1EH031H51H032HFFH 030H1EH031H51H032H05H AT89C51的程序存储器阵列是采用字节写入方式编程的每次写入一个字节要对整个芯片内的PEROM程序存储器写入一个非空字节必须使用片擦除的方式将整个存储器的内容清除编程方法编程前需按表1图3和图4所示设置好地址数据及控制信号AT89C51编程方法如下在地址线上加上要编程单元的地址信号在数据线上加上要写入的数据字节激活相应的控制信号在高电压编程方式时将EAVPP端加上12V编程电压每对FLASH存储阵列写入一个字节或每写入一个程序加密位加上一个ALEPROG编程脉冲改变编程单元的地址和写入的数据重复15步骤直到全部文件编程结束每个字节写入周期是自身定时地通常约为15ms数据查询AT89C51单片机用数据查询方式来检测一个写周期是否结束