数字电子技术(Floyd第十版)课件Chapter2

DigitalFundamentalsTenthEditionFloydChapter9©2008PearsonEducationDigitalFundamentalsChapter9©Ashiftregisterisanarrangementofflip-flopswithimportantapplicationsinstorageandmovementofdata.Somebasicdatamovementsareillustratedhere.SummaryBasicShiftRegisterOperationsDatainDatainDatainDatainDatainDataoutDataoutDataoutDataoutDataoutSerialin/shiftright/serialoutSerialin/shiftleft/serialoutParallelin/serialoutParallelin/paralleloutSerialin/paralleloutRotaterightRotateleftAshiftregisterisanarrangeSummarySerial-in/SerialoutShiftRegisterShiftregistersareavailableinICformorcanbeconstructedfromdiscreteflip-flopsasisshownherewithafive-bitserial-inserial-outregister.Eachclockpulsewillmoveaninputbittothenextflip-flop.Forexample,a1isshownasitmovesacross.111111CLKCLKCLKCLKCLKSummarySerial-in/SerialoutShSummaryABasicApplicationAnapplicationofshiftregistersisconversionofserialdatatoparallelform.Forexample,assumethebinarynumber1011isloadedsequentially,onebitateachclockpulse.CLKCLKCLKCLKAfter4clockpulses,thedataisavailableattheparalleloutput.SummaryABasicApplicationAnaSummaryThe74HC164AShiftRegisterThe74HC164AisaCMOS8-bitserialin/paralleloutshiftregister.VCCcanbefrom+2.0Vto+6.0V.OneofthetwoserialdatainputsmaybeusedasanactiveHIGHenabletogatetheotherinput.Ifnoenableisneeded,theotherserialinputcanbeconnectedtoVCC.The74HC164AhasanactiveLOWasynchronousclear.Dataisenteredontheleading-edgeoftheclock.CLKQ0Q1Q2Q3CLRQ4Q5Q6Q7SerialinputsABSummaryThe74HC164AShiftRegiSummaryWaveformsforthe74HC164ASamplewaveformsforthe74HC164Aareshown.NoticethatBactsasanactiveHIGHenableforthedataonAasdiscussed.CLKQ0Q1Q2Q3CLRQ4Q5Q6Q7SerialinputsABOutputsClearClearAswithCMOSdevices,unusedinputsshouldalwaysbeconnectedtoalogiclevel;unusedoutputsshouldbeleftopen.SummaryWaveformsforthe74HC1SummaryParallelin/SerialoutShiftRegisterShiftregisterscanbeusedtoconvertparalleldatatoserialform.Alogicdiagramforthistypeofregisterisshown:D0D1D2D3Q0Q1Q2Q3SHIFT/LOADCLKSerialdataoutSummaryParallelin/SerialoutSummaryThe74HC165ShiftRegisterThe74HC165isaCMOS8-bitparallelin/serialoutshiftregister.Thelogicsymbolisshown:D0D1D2D3D4D5D6D7Q7Q7SH/LDCLKSERCLKINHTheclock(CLK)andclockinhibit(CLKINH)linesareconnectedtoacommonORgate,soeitheroftheseinputscanbeusedasanactive-LOWclockenablewiththeotherastheclockinput.DataisloadedasynchronouslywhenSH/LDisLOWandmovedthroughtheregistersynchronouslywhenSH/LDisHIGHandarisingclockpulseoccurs.SummaryThe74HC165ShiftRegisSummaryThe74HC165ShiftRegisterAMultisimsimulationofthe74165Aisshown.Thewordgeneratorisusedasasourceforthepatternshowninthegreenprobes.MSBPatternisloadedwhenJ1isLOWQ7islabeledQHinMultisimSummaryThe74HC165ShiftRegisSummaryThe74HC165ShiftRegisterHerethescopeisopenedandyoucanobservethepattern.TheMSBisHIGHandisontheQ7outputassoonasLOADisLOW.LoadQ7ClkMSBSummaryThe74HC165ShiftRegisSummaryBidirectionalShiftRegisterBidirectionalshiftregisterscanshiftthedataineitherdirectionusingaRIGHT/LEFTinput.ThelogicanalyzersimulationshowsabidirectionalshiftregistersuchastheoneshowninFigure9-19ofthetext.NoticetheHIGHlevelfromtheSerialdatainisshiftedatfirstfromQ3towardQ0.CLKRIGHT/LEFTSerialdatainQ0Q1Q2Q3Shiftright

ShiftleftSummaryBidirectionalShiftRegSummaryBidirectionalShiftRegisterCLKRIGHT/LEFTSerialdatainQ0Q1Q2Q3Shiftright

ShiftleftQuestionHowwillthepatternchangeiftheRIGHT/LEFTcontrolsignalisinverted?AnswerSeedisplayShiftright

ShiftleftSummaryBidirectionalShiftRegSummaryUniversalShiftRegisterAuniversalshiftregisterhasbothserialandparallelinputandoutputcapability.The74HC194isanexampleofa4-bitbidirectionaluniversalshiftregister.D0D1D2D3CLKSLSERQ0Q1Q2Q3SRSERS1S0CLRSamplewaveformsareonthefollowingslide…SummaryUniversalShiftRegisteSummaryUniversalShiftRegisterSummaryUniversalShiftRegisteSummaryShiftRegisterCountersShiftregisterscanformusefulcountersbyrecirculatingapatternof0’sand1’s.TwoimportantshiftregistercountersaretheJohnsoncounterandtheringcounter.TheJohnsoncountercanbemadewithaseriesofDflip-flops…orwithaseriesofJ-Kflipflops.HereQ3andQ3arefedbacktotheJandKinputswitha“twist”.SummaryShiftRegisterCountersSummaryJohnsonCounter“twist”RedrawingthesameJohnsoncounter(withouttheclockshown)illustrateswhyitissometimescalledasa“twisted-ring”counter.SummaryJohnsonCounter“twist”RSummaryJohnsonCounterTheJohnsoncounterisusefulwhenyouneedasequencethatchangesbyonlyonebitatatimebutithasalimitednumberofstates(2n,wheren=numberofstages).Thefirstfivecountsfora4-bitJohnsoncounterthatisinitiallyclearedare: CLK Q0

Q1

Q2

Q300001 00011001110111101110011000101234567Whataretheremaining3states?QuestionSummaryJohnsonCounterTheJohnSummaryRingCounterTheringcountercanalsobeimplementedwitheitherDflip-flopsorJ-Kflip-flops.Hereisa4-bitringcounterconstructedfromaseriesofDflip-flops.Noticethefeedback.LiketheJohnsoncounter,itcanalsobeimplementedwithJ-Kflipflops.SummaryRingCounterTheringcoSummaryRingCounterRedrawingtheRingcounter(withouttheclockshown)showswhyitisa“ring”.Thedisadvantagetothiscounteristhatitmustbepreloadedwiththedesiredpattern(usuallyasingle0or1)andithasevenfewerstatesthanaJohnsoncounter(n,wheren=numberofflip-flops.Ontheotherhand,ithastheadvantageofbeingself-decodingwithauniqueoutputforeachstate.SummaryRingCounterRedrawingtSummaryRingCounterAcommonpatternforaringcounteristoloaditwithasingle1orasingle0.Thewaveformsshownhereareforan8-bitringcounterwithasingle1.SummaryRingCounterAcommonpaSummaryShiftRegisterApplicationsShiftregisterscanbeusedtodelayadigitalsignalbyapredeterminedamount.ExampleAn8-bitserialin/serialoutshiftregisterhasa40MHzclock.Whatisthetotaldelaythroughtheregister?SolutionThedelayforeachclockis1/40MHz=25nsThetotaldelayis8x25ns=200ns25ns=200nsSummaryShiftRegisterApplicatSummaryShiftRegisterApplicationsAUART(UniversalAsynchronousReceiverTransmitter)isaserial-to-parallelconverterandaparalleltoserialconverter.UARTsarecommonlyusedinsmallsystemswhereonedevicemustcommunicatewithanother.Paralleldataisconvertedtoasynchronousserialformandtransmitted.Theserialdataformatis:StartBit(0)StopBits(1)DatabusSerialdatainSerialdataoutCLKCLKSummaryShiftRegisterApplicatSummaryKeyboardEncoderThekeyboardencoderisanexampleofwherearingcounterisusedinasmallsystemtoencodeakeypress.Two74HC195shiftregistersareconnectedasan8-bitringcounterpreloadedwithasingle0.Asthe0circulateintheringcounter,it“scans”thekeyboardlookingforanyrowthathasakeyclosure.Whenoneisfound,acorrespondingcolumnlineisconnectedtothatrowline.Thecombinationoftheuniquecolumnandrowlinesidentifiesthekey.Theschematicisshownonthefollowingslide…SummaryKeyboardEncoderThekey©2008PearsonEducation©2008PearsonEducationKeyTerms

RegisterStageShiftLoadBidirectionalOneormoreflip-flopsusedtostoreandshiftdata.Onestorageelementinaregister.Tomovebinarydatafromstagetostagewithinashiftregisterorotherstoragedeviceortomovebinarydataintooroutofthedevice.Toenterdatainashiftregister.Havingtwodirections.Inabidirectionalshiftregister,thestoreddatacanbeshiftedrightorleft.KeyTermsRegisterOneormor1.Theshiftregisterthatwouldbeusedtodelayserialdataby4clockperiodsis a. c. b. d.©2008PearsonEducationQuiz1.Theshiftregisterthatwo©2008PearsonEducationQuiz2. Thecircuitshownisa a.serial-in/serial-outshiftregister

b.serial-in/parallel-outshiftregister c.parallel-in/serial-outshiftregister d.parallel-in/parallel-outshiftregister©2008PearsonEducationQuiz2.Quiz3. IftheSHIFT/LOADlineisHIGH,data a.isloadedfromD0,D1,D2andD3immediately b.isloadedfromD0,D1,D2andD3onthenextCLK c.shiftedfromlefttorightonthenextCLK

d.shiftedfromrighttoleftonthenextCLK©2008PearsonEducationQuiz3. IftheSHIFT/LOADline©2008PearsonEducationQuiz4. A4-bitparallel-in/parallel-outshiftregisterwillstoredatafor a.1clockperiod b.2clockperiods c.3clockperiods

d.4clockperiods©2008PearsonEducationQuiz4.5.The74HC164(shown)hastwoserialinputs.IfdataisplacedontheAinput,theBinput a.couldserveasanactiveLOWenable b.couldserveasanactiveHIGHenable c.shouldbeconnectedtoground d.shouldbeleftopen©2008PearsonEducationQuizCLKQ0Q1Q2Q3CLRQ4Q5Q6Q7SerialinputsAB5.The74HC164(shown)hastwoQuiz6. AnadvantageofaringcounteroveraJohnsoncounteristhattheringcounter a.hasmorepossiblestatesforagivennumberofflip-flops b.isclearedaftereachcycle c.allowsonlyonebittochangeatatime

d.isself-decoding

Quiz6. AnadvantageofaringQuiz7. Apossiblesequencefora4-bitringcounteris a.…1111,1110,1101…

b.…0000,0001,0010… c.…0001,0011,0111…

d.…1000,0100,0010…Quiz7. ApossiblesequenceforQuiz8. Thecircuitshownisa a.serial-in/parallel-outshiftregister b.serial-in/serial-outshiftregister c.ringcounter

d.JohnsoncounterQuiz8. Thecircuitshownisa9.Assumeserialdataisappliedtothe8-bitshiftregistershown.Theclockfrequencyis20MHz.Thefirstdatabitwillshowupattheoutputin a.50ns b.200ns c.400ns d.800ns©2008PearsonEducationQuiz9.Assumeserialdataisappli10.Fortransmission,datafromaUARTissentin a.asynchronousserialform b.synchronousparallelform c.canbeeitheroftheabove d.noneoftheabove©2008PearsonEducationQuiz10.Fortransmission,datafroAnswers:1.a2.c3.c4.a5.b6.d7.d8.d9.c10.aQuizAnswers:6.dQuizDigitalFundamentalsTenthEditionFloydChapter9©2008PearsonEducationDigitalFundamentalsChapter9©Ashiftregisterisanarrangementofflip-flopswithimportantapplicationsinstorageandmovementofdata.Somebasicdatamovementsareillustratedhere.SummaryBasicShiftRegisterOperationsDatainDatainDatainDatainDatainDataoutDataoutDataoutDataoutDataoutSerialin/shiftright/serialoutSerialin/shiftleft/serialoutParallelin/serialoutParallelin/paralleloutSerialin/paralleloutRotaterightRotateleftAshiftregisterisanarrangeSummarySerial-in/SerialoutShiftRegisterShiftregistersareavailableinICformorcanbeconstructedfromdiscreteflip-flopsasisshownherewithafive-bitserial-inserial-outregister.Eachclockpulsewillmoveaninputbittothenextflip-flop.Forexample,a1isshownasitmovesacross.111111CLKCLKCLKCLKCLKSummarySerial-in/SerialoutShSummaryABasicApplicationAnapplicationofshiftregistersisconversionofserialdatatoparallelform.Forexample,assumethebinarynumber1011isloadedsequentially,onebitateachclockpulse.CLKCLKCLKCLKAfter4clockpulses,thedataisavailableattheparalleloutput.SummaryABasicApplicationAnaSummaryThe74HC164AShiftRegisterThe74HC164AisaCMOS8-bitserialin/paralleloutshiftregister.VCCcanbefrom+2.0Vto+6.0V.OneofthetwoserialdatainputsmaybeusedasanactiveHIGHenabletogatetheotherinput.Ifnoenableisneeded,theotherserialinputcanbeconnectedtoVCC.The74HC164AhasanactiveLOWasynchronousclear.Dataisenteredontheleading-edgeoftheclock.CLKQ0Q1Q2Q3CLRQ4Q5Q6Q7SerialinputsABSummaryThe74HC164AShiftRegiSummaryWaveformsforthe74HC164ASamplewaveformsforthe74HC164Aareshown.NoticethatBactsasanactiveHIGHenableforthedataonAasdiscussed.CLKQ0Q1Q2Q3CLRQ4Q5Q6Q7SerialinputsABOutputsClearClearAswithCMOSdevices,unusedinputsshouldalwaysbeconnectedtoalogiclevel;unusedoutputsshouldbeleftopen.SummaryWaveformsforthe74HC1SummaryParallelin/SerialoutShiftRegisterShiftregisterscanbeusedtoconvertparalleldatatoserialform.Alogicdiagramforthistypeofregisterisshown:D0D1D2D3Q0Q1Q2Q3SHIFT/LOADCLKSerialdataoutSummaryParallelin/SerialoutSummaryThe74HC165ShiftRegisterThe74HC165isaCMOS8-bitparallelin/serialoutshiftregister.Thelogicsymbolisshown:D0D1D2D3D4D5D6D7Q7Q7SH/LDCLKSERCLKINHTheclock(CLK)andclockinhibit(CLKINH)linesareconnectedtoacommonORgate,soeitheroftheseinputscanbeusedasanactive-LOWclockenablewiththeotherastheclockinput.DataisloadedasynchronouslywhenSH/LDisLOWandmovedthroughtheregistersynchronouslywhenSH/LDisHIGHandarisingclockpulseoccurs.SummaryThe74HC165ShiftRegisSummaryThe74HC165ShiftRegisterAMultisimsimulationofthe74165Aisshown.Thewordgeneratorisusedasasourceforthepatternshowninthegreenprobes.MSBPatternisloadedwhenJ1isLOWQ7islabeledQHinMultisimSummaryThe74HC165ShiftRegisSummaryThe74HC165ShiftRegisterHerethescopeisopenedandyoucanobservethepattern.TheMSBisHIGHandisontheQ7outputassoonasLOADisLOW.LoadQ7ClkMSBSummaryThe74HC165ShiftRegisSummaryBidirectionalShiftRegisterBidirectionalshiftregisterscanshiftthedataineitherdirectionusingaRIGHT/LEFTinput.ThelogicanalyzersimulationshowsabidirectionalshiftregistersuchastheoneshowninFigure9-19ofthetext.NoticetheHIGHlevelfromtheSerialdatainisshiftedatfirstfromQ3towardQ0.CLKRIGHT/LEFTSerialdatainQ0Q1Q2Q3Shiftright

ShiftleftSummaryBidirectionalShiftRegSummaryBidirectionalShiftRegisterCLKRIGHT/LEFTSerialdatainQ0Q1Q2Q3Shiftright

ShiftleftQuestionHowwillthepatternchangeiftheRIGHT/LEFTcontrolsignalisinverted?AnswerSeedisplayShiftright

ShiftleftSummaryBidirectionalShiftRegSummaryUniversalShiftRegisterAuniversalshiftregisterhasbothserialandparallelinputandoutputcapability.The74HC194isanexampleofa4-bitbidirectionaluniversalshiftregister.D0D1D2D3CLKSLSERQ0Q1Q2Q3SRSERS1S0CLRSamplewaveformsareonthefollowingslide…SummaryUniversalShiftRegisteSummaryUniversalShiftRegisterSummaryUniversalShiftRegisteSummaryShiftRegisterCountersShiftregisterscanformusefulcountersbyrecirculatingapatternof0’sand1’s.TwoimportantshiftregistercountersaretheJohnsoncounterandtheringcounter.TheJohnsoncountercanbemadewithaseriesofDflip-flops…orwithaseriesofJ-Kflipflops.HereQ3andQ3arefedbacktotheJandKinputswitha“twist”.SummaryShiftRegisterCountersSummaryJohnsonCounter“twist”RedrawingthesameJohnsoncounter(withouttheclockshown)illustrateswhyitissometimescalledasa“twisted-ring”counter.SummaryJohnsonCounter“twist”RSummaryJohnsonCounterTheJohnsoncounterisusefulwhenyouneedasequencethatchangesbyonlyonebitatatimebutithasalimitednumberofstates(2n,wheren=numberofstages).Thefirstfivecountsfora4-bitJohnsoncounterthatisinitiallyclearedare: CLK Q0

Q1

Q2

Q300001 00011001110111101110011000101234567Whataretheremaining3states?QuestionSummaryJohnsonCounterTheJohnSummaryRingCounterTheringcountercanalsobeimplementedwitheitherDflip-flopsorJ-Kflip-flops.Hereisa4-bitringcounterconstructedfromaseriesofDflip-flops.Noticethefeedback.LiketheJohnsoncounter,itcanalsobeimplementedwithJ-Kflipflops.SummaryRingCounterTheringcoSummaryRingCounterRedrawingtheRingcounter(withouttheclockshown)showswhyitisa“ring”.Thedisadvantagetothiscounteristhatitmustbepreloadedwiththedesiredpattern(usuallyasingle0or1)andithasevenfewerstatesthanaJohnsoncounter(n,wheren=numberofflip-flops.Ontheotherhand,ithastheadvantageofbeingself-decodingwithauniqueoutputforeachstate.SummaryRingCounterRedrawingtSummaryRingCounterAcommonpatternforaringcounteristoloaditwithasingle1orasingle0.Thewaveformsshownhereareforan8-bitringcounterwithasingle1.SummaryRingCounterAcommonpaSummaryShiftRegisterApplicationsShiftregisterscanbeusedtodelayadigitalsignalbyapredeterminedamount.ExampleAn8-bitserialin/serialoutshiftregisterhasa40MHzclock.Whatisthetotaldelaythroughtheregister?SolutionThedelayforeachclockis1/40MHz=25nsThetotaldelayis8x25ns=200ns25ns=200nsSummaryShiftRegisterApplicatSummaryShiftRegisterApplicationsAUART(UniversalAsynchronousReceiverTransmitter)isaserial-to-parallelconverterandaparalleltoserialconverter.UARTsarecommonlyusedinsmallsystemswhereonedevicemustcommunicatewithanother.Paralleldataisconvertedtoasynchronousserialformandtransmitted.Theserialdataformatis:StartBit(0)StopBits(1)DatabusSerialdatainSerialdataoutCLKCLKSummaryShiftRegisterApplicatSummaryKeyboardEncoderThekeyboardencoderisanexampleofwherearingcounterisusedinasmallsystemtoencodeakeypress.Two74HC195shiftregistersareconnectedasan8-bitringcounterpreloadedwithasingle0.Asthe0circulateintheringcounter,it“scans”thekeyboardlookingforanyrowthathasakeyclosure.Whenoneisfound,acorrespondingcolumnlineisconnectedtothatrowline.Thecombinationoftheuniquecolumnandrowlinesidentifiesthekey.Theschematicisshownonthefollowingslide…SummaryKeyboardEncoderThekey©2008PearsonEducation©2008PearsonEducationKeyTerms

RegisterStageShiftLoadBidirectionalOneormoreflip-flopsusedtostoreandshiftdata.Onestorageelementinaregister.Tomovebinarydatafromstagetostagewithinashiftregisterorotherstoragedeviceortomovebinarydataintooroutofthedevice.Toenterdatainashiftregister.Havingtwodirections.Inabidirectionalshiftregister,thestoreddatacanbeshiftedrightorleft.KeyTermsRegisterOneormor1.Theshiftregisterthatwouldbeusedtodelayserialdataby4clockperiodsis a. c. b. d.©2008PearsonEducationQuiz1.Theshiftregisterthatwo©2008PearsonEducationQuiz2. Thecircuitshownisa a.serial-in/serial-outshiftregister

b.serial-in/parallel-outshiftregister c.parallel-in/serial-out