计算机组成与结构：chapter13 Reduced Instruction Set Computers

ComputerOrganization&ArchitectureChapter13

ReducedInstructionSetComputersMajorAdvancesinComputersThefamilyconceptIBMSystem/360(1964),

andthenDECPDP-8SamearchitecturebutdifferentimplementationsMicroporgrammedcontrolunitIdeabyWilkes1951ProducedbyIBMS/3601964CachememoryIBMS/360model851969MicroprocessorsIntel40041971PipeliningIntroducesparallelismintofetchexecutecycleMultipleprocessorsTheNextStep-RISCWhatisRISCReducedInstructionSetComputerKeyfeaturesLargenumberofgeneralpurposeregistersoruseofcompilertechnologytooptimizeregisteruseLimitedandsimpleinstructionsetwithafixedformatEmphasisonoptimizingtheinstructionpipelineComparisonofprocessors13.1InstructionexecutioncharacteristicsDrivingforceforCISCSoftwarecostsfarexceedhardwarecostsIncreasinglycomplexhighlevellanguages(HLL)SemanticgapLeadstoLargeinstructionsetsMoreaddressingmodesHardwareimplementationsofHLLstatementsIntentionofCISCEasecompilerwritingImproveexecutionefficiencyComplexoperationsinmicrocodeSupportmorecomplexHLLsExecutionCharacteristicsOperationsperformedOperandsusedExecutionsequencingStudieshavebeendonebasedonprogramswritteninHLLsDynamicstudiesaremeasuredduringtheexecutionoftheprogramOperationsAssignmentsMovementofdataConditionalstatements(IF,LOOP)SequencecontrolProcedurecall-returnisverytimeconsumingSomeHLLinstructionleadtomanymachinecodeoperationsOperandsMainlylocalscalarvariablesOptimisationshouldconcentrateonaccessinglocalvariablesProcedureCallsVerytimeconsumingDependsonnumberofparameterspassedDependsonlevelofnestingThenumberofwordsusedbyperprocedurecallisnotlargeMostvariablesarelocalMostprogramsdonotdoalotofcallsfollowedbylotsofreturns(c.f.localityofreference)ImplicationsBestsupportisgivenbyoptimisingmostusedandmosttimeconsumingfeaturesLargenumberofregistersOperandreferencingCarefuldesignofpipelinesBranchpredictionetc.Simplified(reduced)instructionset13.2TheuseofalargeregisterfileRegisterFeatures:Fasterthancache,memoryShorteraddressNearCPUSoftwaresolutionRequirecompilertoallocateregistersAllocatebasedonmostusedvariablesinagiventimeRequiressophisticatedprogramanalysisHardwaresolutionHavemoreregistersThusmorevariableswillbeinregistersRegistersforLocalVariablesStorelocalscalarvariablesinregistersReducesmemoryaccessEveryprocedure(function)callchangeslocalityParametersmustbepassedResultsmustbereturnedVariablesfromcallingprogramsmustbestoredtoregistersRegisterWindowsTypically,

aprocedureemploys:OnlyfewparametersandlocalvariablesLimitedrangeofdepthofcallUsemultiplesmallsetsofregisters,eachassignedtoadifferentprocedureawindowforaprocedureCallsswitchtoadifferentsetofregisters,

ratherthansavingcontentsofregistersintomemoryWindowsforadjacentproceduresareoverlappedtoallowparameterpassingReturnsswitchbacktoapreviouslyusedsetofregisters

OverlappingRegisterWindowsRegisterWindowsContents.ThreeareaswithinaregistersetParameterregistersLocalregistersTemporaryregistersTemporaryregistersfromonesetoverlapparameterregistersfromthenextThisallowsparameterpassingwithoutmovingdataCircular-BufferOrganizationofOverlappedWindows

OperationofCircularSetsofRegisterWhenacallismade,acurrentwindowpointerismovedtoshowthecurrentlyactiveregisterwindowIfallwindowsareinuse,aninterruptisgeneratedandtheoldestwindow(theonefurthestbackinthecallnesting)issavedtomemoryAsavedwindowpointerindicateswherethenextsavedwindowsshouldrestoretoN-windowscanholdonlyN-1procedurecalls.Typically,8windowsof16registerseachisadoptedBerkeleyRISCGlobalVariablesIfwedeclaresomevariablesasglobalinaHLL,atypicalmethodisAllocatedbythecompilertomemoryInefficientforfrequentlyaccessedvariablesTheotheristohaveasetofregistersforglobalvariablesDoitbycompilerLargeRegistersvCacheTheregisters,organizedintowindows,actasasmall,fastbufferforholdingasubsetofallvariablesFromthisviewpoint,theregistersetismuchlikeacacheWhoisbetter?FeatureCompareofRegisterSetAndCacheSpecificationsforRegisterSetAndCacheWindows-basedregistersarefaster,butcachemaymakemoreefficientuseofspace,becauseitisreactingtothesituationdynamicallyCachemaysufferfromanothersortofinefficiency:dataarereadintoinblock,someofwhichwillnotbeusedInregisterfile,usingmemoryisrelativelyin-frequently,setassociativecachewillsufferfromoverwritingusedvariablesRegisterfileisshorteraddressingmode,fasterthancacheIngeneral,registerfileissuperiorforvariables

ReferencingaScalar-WindowBasedRegisterFileReferencingaScalar-Cache

13.3CompilerBasedRegisterOptimizationLargeregistersetcanimproveperformanceofacomputer,howaboutasmallnumberofregisters?Assumesmallnumberofregisters(16-32)inRISC,wecanobtainahighperformancealsobyusingoptimizedregistersOptimizationisdonebytheRISCcompilerHowtoOptimize?HLLprogramshavenoexplicitreferencestoregistersusually-thinkaboutC-registerintAssignsymbolicorvirtualregistertoeachcandidatevariableMap(unlimited)symbolicregisterstorealregistersSymbolicregistersthatdonotoverlapcansharerealregistersIfyourunoutofrealregisterssomevariablesusememory,

andso,load-and-storeDRAMoperationsareminimizedRegistersOptimizationbasedonGraphColoringTheessenceoftheoptimizationistodecidewhichvariablescanuseregistersatanygivenpointinaprogramThetechniquemostcommonlyusedinRISCcompilerisgraphcoloringDefinition:givenagraphconsistingofnodesandedges,assigncolorstonodessuchthatadjacentnodeshavedifferentcolors,andthenumberofcolorsareminimized.Thenodesaresymbolicregisters,iftwosymbolicregistersare“live”duringthesameprogramfragment,theyarejoinedbyanedgetodepictinterferenceTrytocolorthegraphwithn

colors,wherenisthenumberofrealregistersColorsrepresentsthenumberofphysicalregistersThesamecolormeansthesameregisterIfthisprocessdoesnotfullysucceed,thenthosenodesthatcannotbecoloredmustbeplacedinmemory

ADGraphColoringApproach13.4ReducedinstructionsetarchitectureWhyCISC?Compilersimplification?Disputed…ComplexmachineinstructionshardertoexploitOptimizationmoredifficultSmallerprograms?Programtakesuplessmemorybut…MemoryisnowcheapMaynotoccupylessbits,justlookshorterinsymbolicformMoreinstructionsrequirelongerop-codesRegisterreferencesrequirefewerbitsFasterprograms?BiastowardsuseofsimplerinstructionsMorecomplexcontrolunitMicroprogramcontrolstorelargerthussimpleinstructionstakelongertoexecuteItisfarfromclearthatCISCistheappropriatesolutionRISCCharacteristicsOneinstructionpercycleRegistertoregisteroperationsFew,simpleaddressingmodesFew,simple,fixedinstructionformatsHardwireddesign(nomicrocode)EffectivelyinstructionpipeliningMoreresponsivetointerruptMorecompiletime/effortRISCvCISCNotclearcut,

fightingisstillgoingonManydesignsborrowfrombothphilosophiese.g.PowerPCandPentiumII13.5RISCPipeliningMostinstructionsareregistertoregisterTwophasesofexecutionI:InstructionfetchE:ExecuteForloadandstore,

threephasesarerequired:I:InstructionfetchE:ExecuteCalculatememoryaddressD:MemoryRegistertomemoryormemorytoregisteroperationTheEffectsofPipeliningOptimizationofPipelining2Concepts:DelayedbranchDoesnottakeeffectuntilafterexecutionoffollowinginstructionThisfollowinginstructionisthedelayslotNormal,DelayedandOptimizedBranch

Address

Normal

Delayed Optimized

100

LOADX,A

LOADX,A LOADX,A

101

ADD1,AADD1,A JUMP105

102

JUMP105

JUMP106 ADD1,A

103

ADDA,B NOOP

ADDA,B

104

SUBC,B

ADDA,B SUBC,B

105

STOREA,Z SUBC,B STOREA,Z

106 STOREA,Z

Use

of

DelayedBranch13.7SPARCSPARC(scalableprocessorarchitecture)AnprocessorarchitecturedefinedanddevelopedbySUNMachinewiththisprocessorrefersastoSPARCworkstationSPARC10,SPARC20SPARCRegisterSetUsingregisterwindows2~32windowsEachwindowhas24registersPhysicalregisters0~7areglobalregisterssharedbyallprocedures8registersareusedforparameterspassing8registersareusedforresultsreturning8localregistersareusedfortheprocedure

WindowInvalidMaskCurrentWindowPointer8RegistersWindowsinSPARCInstructionSetInSPARCset,mostofinstructionreferenceonlyregisteroperands,goodforahighproportionoflocalscalarsandconstantsRd

Rs1ops2ALUoperationsgroupedasfollows:Integeraddition(withorwithoutcarry)Integersubtraction(withorwithoutcarry)LogicalopShiftlogicorarithmeticSeetable13.12,noneedforrememberingDisplacementaddressingandsimpleaddressingmodes(seetable13.13)InstructionFormat32-bitinstructionformatAllbeginwith2-bitopcodeSomeinstructi