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WilliamStallings

ComputerOrganization

andArchitecture

5thEditionChapter13InstructionLevelParallelismandSuperscalarProcessors淘宝刷信誉WhatisSuperscalar?Thetermsuperscalarreferstoamachinethatdesignedtoimprovetheperformanceoftheexecutionofscalarinstructions.Therearemultipleindependentinstructionpipelinesinasuperscalarprocessor.Eachpipelineconsistsofmultiplestages,canhandlemultipleinstructionsatatime.Multiplepipelinesintroduceanewlevelofparallelism,enablingmultiplestreamsofinstructionstobeprocessedatatime.WhatisSuperscalar?AsuperscalarprocessorfetchesmultipleinstructionsatatimeAttemptstofindnearbyinstructionsthatareindependentofoneanotherandcanbeexecutedinparallel.Theessenceofthesuperscalarapproachistheabilitytoexecuteinstructionsindependentlyindifferentpipelines.WhatisSuperscalar?Commoninstructions(arithmetic,load/store,conditionalbranch)canbeinitiatedandexecutedindependentlyinasuperscalarprocessorEquallyapplicabletoRISC&CISCInpracticeusuallyRISCWhySuperscalar?Mostoperationsareonscalarquantities(seeRISCnotes)ImprovetheseoperationstogetanoverallimprovementGeneralSuperscalarOrganizationTwointeger,twofloating-point,andonememory(eitherloadorstore)operationscanbeexecutingatthesametime.SuperpipelinedManypipelinestagesneedlessthanhalfaclockcycleDoubleinternalclockspeedgetstwotasksperexternalclockcycleSuperscalarv

SuperpipelineSuperscalarvSuperpipelineBasemachineSuperscalarvSuperpipelineSuperpipelineSuperscalarvSuperpipelineSuperscalarLimitationsInstructionlevelparallelismCompilerbasedoptimisationHardwaretechniquesLimitedbyTruedatadependency 数据相关Proceduraldependency 过程相关Resourceconflicts 资源冲突Outputdependency 输出相关Antidependency 反相关TrueDataDependencyADDr1,r2(r1:=r1+r2;)MOVEr3,r1(r3:=r1;)CanfetchanddecodesecondinstructioninparallelwithfirstCanNOTexecutesecondinstructionuntilfirstisfinishedAlsocalledflowdependency

orwrite-readdependencyTrueDataDependencyProceduralDependencyCannotexecuteinstructionsafterabranchinparallelwithinstructionsbeforeabranchAlso,ifinstructionlengthisnotfixed,instructionshavetobedecodedtofindouthowmanyfetchesareneededThispreventssimultaneousfetchesProceduralDependencyResourceConflictResourcesMemories,caches,buses,register-file,ports,functionalunitsTwoormoreinstructionsrequiringaccesstothesameresourceatthesametimee.g.twoarithmeticinstructionsCanduplicateresourcese.g.havetwoarithmeticunitsResourceConflictEffectof

DependenciesDesignIssuesInstructionlevelparallelismInstructionsinasequenceareindependentExecutioncanbeoverlappedGovernedbydataandproceduraldependencyMachineParallelismAbilitytotakeadvantageofinstructionlevelparallelism处理器提供指令级并行性支持能力的度量GovernedbynumberofparallelpipelinesE.g.LoadR1R2(23) AddR3R3,”1”AddR3R3,”1” AddR4R3,R2AddR4R4,R2 Store[R4]R0InstructionIssuePolicy(指令发射策略)Orderinwhichinstructionsarefetched取指令的顺序Orderinwhichinstructionsareexecuted指令执行的顺序Orderinwhichinstructionschangeregistersandmemory指令改变寄存器和存储器内容的顺序In-OrderIssue

In-OrderCompletionIssueinstructionsintheordertheyoccurNotveryefficientMayfetch>1instructionInstructionsmuststallifnecessaryIn-OrderIssueIn-OrderCompletion(Diagram)In-OrderIssue

Out-of-OrderCompletionOutputdependencyR3:=R3+R5;(I1)R4:=R3+1;(I2)R3:=R5+1;(I3)I2dependsonresultofI1-datadependencyIfI3completesbeforeI1,theresultfromI1willbewrong-output(read-write)dependencyIn-OrderIssueOut-of-OrderCompletion(Diagram)Out-of-OrderIssue

Out-of-OrderCompletionDecoupledecodepipelinefromexecutionpipelineCancontinuetofetchanddecodeuntilthispipelineisfullWhenafunctionalunitbecomesavailableaninstructioncanbeexecutedSinceinstructionshavebeendecoded,processorcanlookaheadOut-of-OrderIssueOut-of-OrderCompletion(Diagram)AntidependencyWrite-writedependencyR3:=R3+R5;(I1)R4:=R3+1;(I2)R3:=R5+1;(I3)R7:=R3+R4;(I4)I3cannotcompletebeforeI2startsasI2needsavalueinR3andI3changesR3RegisterRenamingOutputandantidependenciesoccurbecauseregistercontentsmaynotreflectthecorrectorderingfromtheprogramMayresultinapipelinestallRegistersallocateddynamicallyi.e.registersarenotspecificallynamedRegisterRenamingexampleRegisterrenamingR3b:=R3a+R5a(I1)R4b:=R3b+1(I2)R3c:=R5a+1(I3)R7b:=R3c+R4b(I4)WithoutsubscriptreferstologicalregisterininstructionWithsubscriptishardwareregisterallocatedNoteR3aR3bR3cMachineParallelismThreehardwaretechniquesDuplicationofResourcesOutoforderissueRenamingFigure13.5showssimulationresultsNotworthduplicationfunctionswithoutregisterrenamingRegisterrenamingeliminatesantidependenciesandoutputdependenciesNeedinstructionwindowlargeenough(morethan8)BranchPrediction80486fetchesbothnextsequentialinstructionafterbranchandbranchtargetinstructionGivestwocycledelayifbranchtakenRISC-DelayedBranchCalculateresultofbranchbeforeunusableinstructionspre-fetchedAlwaysexecutesingleinstructionimmediatelyfollowingbranchKeepspipelinefullwhilefetchingnewinstructionstreamNotasgoodforsuperscalarMultipleinstructionsneedtoexecuteindelayslotInstructiondependenceproblemsReverttobranchpredictionSuperscalarExecutionSuperscalarImplementationSimultaneouslyfetchmultipleinstructionsLogictodeterminetruedependenciesinvolvingregistervaluesMechanismstocommunicatethesevaluesMechanismstoinitiatemultipleinstructionsinparallelResourcesforparallelexecutionofmultipleinstructionsMechanismsforcommittingprocessstateincorrectorderPentium480486-CISCPentium–somesuperscalarcomponentsTwoseparateintegerexecutionunitsPentiumPro–FullblownsuperscalarSubsequentmodelsrefine&enhancesuperscalardesignPentium4BlockDiagramPentium4OperationFetchinstructionsformmemoryinorderofstaticprogramTranslateinstructionintooneormorefixedlengthRISCinstructions(micro-operations)Executemicro-opsonsuperscalarpipelinemicro-opsmaybeexecutedoutoforderCommitresultsofmi