vhdl多功能数字万年历

vhdl多功能数字万年历

全部源代码，已调试成功

基本要求：采用VHDL硬件描述语言或者电路图描述的方式完成设

计。

1)设计一个万年历系统，可现实从秒到年的计数功能；

2)由于开仅具备四位数码管，因此需要进行功能切换，即利用开

发板上的一个按键完成小时/分钟月/日、年等三种显示的切换。

3)秒计数采用开发板上独立的LED以秒闪进行显示；

4)同时切换设置模式与显示模式(一个按键完成切换)，完成每个

显示的增减设置(两个按键实现增减)。

说明：基本要求不需要提供闰月识别功能。

发挥要求：

1)提供整点时间报警功能；

2)提供闹钟功能；

3)提供闰月检测功能；

4)以7个独立的LED显示星期。

全部源代码如下，已调试成功

1,将50mhz转为1ms时钟count

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYcountIS

PORT(clk:INSTD_LOGIC;

co:OUTSTD_LOGIC);

ENDcount;

ARCHITECTUREbehavOFcountIS

signalcount1:integerrange0to49999;

BEGIN

PROCESS(clk)

BEGIN

IFrising_edge(clk)THEN

count!<=countl+l;

ifcount1=49999then

countl<=0;co<='l';

elseco<='0';

endif;

endif;

endprocess;

endbehav;

2.秒模块

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYsecondIS

PORT(clk:INSTD_LOGIC;

sec:OUTintegerrange0to59;

miao:outstd_logic;

co:OUTSTD_LOGIC);

ENDsecond;

ARCHITECTUREbehavOFsecondIS

signalsect:integerrange0to59;

signaltemp:integerrange0to1000;

BEGIN

process(clk)

begin

IFrising_edge(clk)THEN

iftemp=1000thentemp<=0;

ifsect=59then

sect<=0;co<=T;

elsesect<=sect+l;co<='0';

endif;

elsetemp<=temp+1;co<='0';

endif;

endif;

endprocess;

process(temp,sect)

begin

iftemp<500then

miao<='l';

elsemiao<='0';

endif;

sec<=sect;

endprocess;

endbehav;

3•分模块

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYcentIS

PORT(clk,seco,centkeyadd,centkeysub:INSTD_LOGIC;

cent:outintegerrange0to59;

co:OUTSTD_LOGIC);

ENDcent;

ARCHITECTUREbehavOFcentIS

signalcentt:integerrange0to59;

begin

process(clk,seco)

begin

ifrising_edge(clk)then

ifseco='l'then

ifcentt=59thencentt<=0;co<='l';

elsecentt<=centt+l;co<='0';

endif;

elsifcentkeyadd='O'then

ifcentt=59thencentt<=0;

elsecentt<=centt+1;

endif;

elsifcentkeysub='O'then

ifcentt=Othencentt<=59;

elsecentt<=centt-1;

endif;

elseco<='0';

endif;

endif;

endprocess;

cent<=centt;

endbehav;

4时模块

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYhourIS

PORT(clk,cento,hourkeyadd,hourkeysub:INSTD_LOGIC;

hour:outintegerrange0to23;

co:OUTSTD_LOGIC);

ENDhour;

ARCHITECTUREbehavOFhourIS

signalhourt:integerrange0to59:=9;

begin

process(clk,cento)

begin

ifrising_edge(clk)then

ifcento=Tthen

ifhourt=23thenhourt<=0;co<='l';

elsehourt<=hourt+1;co<='0';

endif;

elsifhourkeyadd='0'then

ifhourt=23thenhourt<=0;

elsehourt<=hourt+1;

endif;

elsifhourkeysub='0'then

ifhourt=0thenhourt<=23;

elsehourt<=hourt-1;

endif;

elseco<='0';

endif;

endif;

endprocess;

hour<=hourt;

endbehav;

5.日模块

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYdayIS

PORT(clk,houro,daykeyadd,daykeysub:INSTD_LOGIC;

yue:inintegerrange1to31;

day:OUTintegerrange1to31;

co:OUTSTD_LOGIC);

ENDday;

ARCHITECTUREbehavOFdayIS

signaldayt:integerrange0to31:=24;

signalyuet:integerrange1to31;

begin

yuet<=yue;

process(clk,houro)

begin

ifrising_edge(clk)then

ifhouro=Tthen

ifdayt=yuetthendayt<=0;co<=T;

elsedayt<=dayt+1;

endif;

elsifdaykeyadd='O'then

ifdayt=yuetthendayt<=0;

elsedayt<=dayt+1;

endif;

elsifdaykeysub='O'then

ifdayt=Othendayt<=yuet;

elsedayt<=dayt-1;

endif;

elseco<='0';

endif;

endif;

endprocess;

day<=dayt;

endbehav;

6.月模块

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYmonthIS

PORT(clk,dayo,monthkeyadd,monthkeysub,run:INSTD_LOGIC;

month:outintegerrange1to12;

yue:outintegerrange1to31;

co:OUTSTD_LOGIC);

ENDmonth;

ARCHITECTUREbehavOFmonthIS

signalmontht:integerrange1to12:=2;

begin

process(clk,dayo)

begin

ifrising_edge(clk)then

ifdayo='l'then

ifmontht=12thenmontht<=1;co<='1';

elsemontht<=montht+1;

endif;

elsifmonthkeyadd='0'then

ifmontht=12thenmontht<=1;

elsemontht<=montht+1;

endif;

elsifmonthkeysub='0'then

ifmontht=lthenmontht<=12;

elsemontht<=montht-1;

endif;

elseco<='0';

endif;

endif;

endprocess;

month<=montht;

—闰月检测功能

process(montht,run)

begin

CASEmonthtIS

WHEN2=>ifrun='1'thenyue<=29;elseyue<=28;endif;——二月

WHEN3=>yue<=30;

—四月

WHEN6=>yue<=30;

-六月

WHEN9=>yue<=30;

WHENll=>yue<=30;

-H~月

WHENothers=>yue<=31;

ENDCASE;

ENDPROCESS;

ENDbehav;

3•年模块

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYyearIS

PORT(clk,montho,yearkeyadd,yearkeysub:INSTD_LOGIC;

year:outintegerrange0to99;

run:OUTSTD_LOGIC);

ENDyear;

ARCHITECTUREbehavOFyearIS

signalyeart:integerrange0to59:=13;

begin

process(clk,montho)

begin

ifrising_edge(clk)then

ifmontho='rthen

ifyeart=59thenyeart<=0;

elseyeart<=yeart+l;

endif;

elsifyearkeyadd='O'then

ifyeart=59thenyeart<=0;

elseyeart<=yeart+1;

endif;

elsifyearkeysub='O'then

ifyeart=Othenyeart<=59;

elseyeart<=yeart-1;

endif;

endif;

endif;

endprocess;

year<=yeart;

process(yeart)

begin

if(yeartmod4)=0then

run<='l';

elserun<='0';

endif;

endprocess;

endbehav;

9.显示模块

-显示模块

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYdisplayIS

PORT(

sec,cent:inintegerrange0to59;

hour:inintegerrange0to23;

day:inintegerrange1to31;

month:inintegerrange1to12;

year:inintegerrange0to99;

cento,houro,elk,keyO,keyI,key2,key3:INSTD_LOGIC;

dis:OUTSTD_LOGIC_VECTOR(7DOWNTO0);

centkeyadd,centkeysub,hourkeyadd,hourkeysub,daykeyadd,daykeysu

b,monthkeyadd,monthkeysub:outstd_logic;--力口减控制输出

yearkeyadd,yearkeysub:outstd_logic;

dis1en,dis2en,dis3en,dis4en,beep:outstd_logic;--数码管使能，设

置指示，蜂鸣器输出

ledweekend:outstd_logic_vector(6downto0));

ENDdisplay;

ARCHITECTUREbehavOFdisplayIS

typestate_typeis(sO,sI,s2,s3,s4);

signalpre_s,next_s:state_type;

typestateis(cl,c2,c3,c4);

signalpre_c,next_c:state;

constantledO:std_logic_vector(7downto0):="l1000000";

constantledl:std_logic_vector(7downto0):="11111001";

constantled2:std_logic_vector(7downto0):="10100100";

constantled3:std_logic_vector(7downto0):="10110000";

constantled4:std_logic_vector(7downto0):="10011001";

constantled5:std_logic_vector(7downto0):="10010010";

constantled6:std_logic_vector(7downto0):="10000010";

constantled7:std_logic_vector(7downto0):="l1111000";

constantled8:std_logic_vector(7downto0):="10000000";

constantled9:std_logic_vector(7downto0):="10010000";

signalcount1:integerrange0to99;

signalcount2:integerrange0to99;

signalcount3:integerrange0to99;

signalcount4:integerrange0to99;

signalset:std_logic_vector(1downto0):="00";

signalweekend:std_logic_vector(6downto0):="0000001";

signalacentadd,acentsub,ahouradd,ahoursub:std_logic:='0';

signalahour,acent,centadd,centsub,houradd,hoursub:integerrange0to

59;

signalweekendset:std_logic:='1

signal

centl,centh,hourl,hourh,dayl,dayh,monthl,monthh,yearl,yearh:integer

range0to9;

signalsec1,sec2,sec3,sec4,acentl,acenth,ahourl,ahourh:integerrange0

to9;

begin

--界nn转换状态机

process(keyO)

begin

iffalling_edge(keyO)then

pre_s<=next_s;

endif;

endprocess;

-扫描状态机

process(clk)

begin

ifrising_edge(clk)then

pre_c<=next_c;

endif;

endprocess;

process(keyl)

begin

iffalling_edge(key1)then

ifset=2then

set<="00";

else

set<=set+l;

endif;

endif;

endprocess;

centl<=centmod10;centh<=cent/10;

hourl<=hourmod10;hourh<=hourh/10;

dayl<=daymod10;dayh<=day/10;

monthl<=monthmod10;monthh<=month/10;

yearl<=yearmod10;yearh<=year/l0;

acentl<=acentmod10;acenth<=acent/10;

ahourl<=ahourmod10;ahourh<=ahourh/10;

-显示切换状态机

Pl：

process(pre_s,set,centl,centh,hourl,hourh,dayl,dayh,monthl,monthh,yearl,

yearh,key2,key3,acentl,acenth,ahourl,ahourh)

begin

casepre_sis

whensO=>count4<=centl;count3<=centh;--显示时钟

count2<=hourl;countl<=hourh;

next_s<=s1;weekendset<=T;

daykeyadd<='1';daykeysub<='l';monthkeyadd<='l';monthkeysub<='1';

yearkeyadd<='1';yearkeysub<='1';

acentadd<='l';acentsub<='1';ahouradd<='1';ahoursub<='1

ifset=1then

centkeyadd<=key2;centkeysub<=key3;hourkeyadd<='r；hourkeysub<='l'

elsifset=2then

hourkeyadd<=key2;hourkeysub<=key3;centkeyadd<='l';centkeysub<='1'

elsecentkeyadd<='r；centkeysub<='l';

hourkeyadd<='1';hourkeysub<=T;

endif;

whensl=>count4<=dayl;count3<=dayh;--显示日期

count2<=monthl;countl<=monthh;

next_s<=s2;weekendset<='1';

centkeyadd<='l';centkeysub<='1';hourkeyadd<='1';hourkeysub<='1';

yearkeyadd<='1';yearkeysub<='1';

acentadd<='l';acentsub<='1';ahouradd<='1';ahoursub<='1

ifset=lthen

daykeyadd<=key2;daykeysub<=key3;monthkeyadd<='l';monthkeysub<=

T；

elsifset=2then

monthkeyadd<=key2;monthkeysub<=key3;daykeyadd<='r；daykeysub<=

T;

elsedaykeyadd<='1';daykeysub<='1';monthkeyadd<='1';monthkeysub<='1

».

endif;

whens2=>count4<=yearl;count3<=yearh;--显示年份

count2<=0;count1<=2;

next_s<=s3;weekendset<='l';

daykeyadd<='l';daykeysub<='l';monthkeyadd<='1';monthkeysub<='1';

centkeyadd<=T;centkeysub<='1';hourkeyadd<='1';hourkeysub<='1';

acentadd<='l';acentsub<='1ahouradd<='1';ahoursub<='1

ifset=lorset=2thenyearkeyadd<=key2;yearkeysub<=key3;

elseyearkeyadd<='1';yearkeysub<='1

endif;

whens3=>count4<=l;count3<=l;--星期控制状态

count2<=1;count1<=1;

next_s<=s4;

daykeyadd<='1';daykeysub<='l';monthkeyadd<='l';monthkeysub<='1';

centkeyadd<='l';centkeysub<='1';hourkeyadd<='1';hourkeysub<='1';

acentadd<='l';acentsub<='1';ahouradd<='1';ahoursub<='1

yearkeyadd<='1';yearkeysub<='1weekendset<='O';

whens4=>count4<=acentl;count3<=acenth;--闹钟设置

状态

count2<=ahourl;countl<=ahourh;

next_s<=sO;

daykeyadd<='1';daykeysub<='l';monthkeyadd<='l';monthkeysub<='1';

centkeyadd<='l';centkeysub<='1';hourkeyadd<='1';hourkeysub<='1';

yearkeyadd<='1';yearkeysub<='1weekendset<='1

ifset=lthenacentadd<=key2;acentsub<=key3;

ahouradd<='r；ahoursub<='l';

elsifset=2then

ahouradd<=key2;ahoursub<=key3;acentadd<='l';acentsub<=T;

elseacentadd<='1';acentsub<='l';ahouradd<='r；ahoursub<='l';

endif;

endcase;

endprocess;

-闹钟功能

process(clk,acent,centadd,centsub)

begin

ifrising_edge(clk)then

ifacent=59then

acent<=0;

else

acent<=centadd-centsub;

endif;

endif;

endprocess;

process(acentadd)

begin

iffalling_edge(acentadd)then

ifacent<60then

centadd<=centadd+1;

elsecentadd<=0;

endif;

endif;

endprocess;

process(acentsub)

begin

iffalling_edge(acentsub)then

ifacent<60then

ifacent>0then

centsub<=centsub+1;

elsenull;

endif;

elsecentsub<=0;

endif;

endif;

endprocess;

process(clk,ahour,houradd,hoursub)

begin

ifrising_edge(clk)then

ifahour=23then

ahour<=0;

elseahour<=houradd-hoursub;

endif;

endif;

endprocess;

process(ahouradd)

begin

iffalling_edge(ahouradd)then

ifahour<23then

houradd<=houradd+1;

elsehouradd<=0;

endif;

endif;

endprocess;

process(ahoursub)

begin

iffalling_edge(ahoursub)then

ifahour<23then

ifahour>0then

hoursub<=hoursub+l;

elsenull;

endif;

elsehoursub<=0;

endif;

endif;

endprocess;

-闹钟

process(clk,cent,hour,acent,ahour)

variableacount:integerrange0to30;

begin

ifrising_edge(clk)then

ifacent=centandahour=hourthen

beep<='0';

elsifcento=Tthen

beep<='0';

elsebeep<=T;

endif;

endif;

endprocess;

-星期显示和设置

process(weekendset,clk,key2,key3)

begin

ifrising_edge(clk)then

ifweekend="0000000"then

weekend<="0000001";

elsifhouro=Tthen

weekend<=weekend(5downto0)&'0';

elsifweekendset='O'then

ifkey2='O'then

weekend<=weekend(5downto0)&'0';

elsifkey3='O'then

weekend<='0'&weekend(6downto1);

endif;

elsenull;

endif;

endif;

endprocess;

ledweekend<=weekend;

p3:process(pre_c,count4,count3,count2,countl)

begin

casepre_cis

whencl=>next_c<=c2;

dis1en<='1';dis2en<='l';dis3en<='l';dis4en<='0';

casecount4is

when0=>dis<=ledO;

when1=>dis<=ledl;

when2=>dis<=led2;

when3=>dis<=led3;

when4=>dis<=led4;

when5=>dis<=led5;

when6=>dis<=led6;

when7=>dis<=led7;

when8=>dis<=led8;

when9=>dis<=led9;

whenothers=>dis<=ledO;

endcase;

whenc2=>

next_c<=c3;

dislen<='l';dis2en<='1';dis3en<='0';dis4en<='1';

casecount3is

when0=>dis<=ledO;

when1=>dis<=ledl;

when2=>dis<=led2;

when3=>dis<=led3;

when4=>dis<=led4;

when5=>dis<=led5;

when6=>dis<=led6;

when7=>dis<=led7;

when8=>dis<=led8;

when9=>dis<=led9;

whenothers=>dis<=ledO;

endcase;

whenc3=>

next_c<=c4;

dis1en<='1';dis2en<='0';dis3en<='l';dis4en<='1';

casecount?is

when0=>dis<=ledO;

when1=>dis<=ledl;

when2=>dis<=led2;

when3=>dis<=led3;

when4=>dis<=led4;

when5=>dis<=led5;

when6=>dis<=led6;

when7=>dis<=led7;

when8=>dis<=led8;

when9=>dis<=led9;

whenothers=>dis<=ledO;

endcase;

whenc4=>

next_c<=cl;

dis1en<='0';dis2en<='1';dis3en<='l';dis4en<='1';

casecount1is

when0=>dis<=ledO;

when1=>dis<=ledl;

when2=>dis<=led2;

when3=>dis<=led3;

when4=>dis<=led4;

when5=>dis<=led5;

when6=>dis<=led6;

when7=>dis<=led7;

when8=>dis<=led8;

when9=>dis<=led9;

whenothers=>dis<=ledO;

endcase;

endcase;

endprocess;

endbehav;

10.顶层文件

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYcalendarIS

PORT(clk,keyO,key1,key2,key3:INSTD_LOGIC;

disIen,dis2en,dis3en,dis4en,setled,beep:outstd_logic;

dis:OUTSTD_LOGIC_VECTOR(7DOWNTO0);

ledweekend:outstd_logic_vector(6downto0));

ENDcalendar;

ARCHITECTUREbehavOFcalendarIS

componentkey

PORT(CLK,kin:INSTD_LOGIC;

kout:OUTSTD_LOGIC);

ENDcomponent;

componentcount

PORT(clk:INSTD_LOGIC;

co:OUTSTD_LOGIC);

ENDcomponent;

componentsecond

PORT(clk:INSTD_LOGIC;

sec:OUTintegerrange0to59;

miao:outstd_logic;

co:OUTSTD_LOGIC);

ENDcomponent;

componentcent

PORT(clk,seco,centkeyadd,centkeysub:INSTD_LOGIC;

cent:outintegerrange0to59;

co:OUTSTD_LOGIC);

ENDcomponent;

componenthour

PORT(clk,cento,hourkeyadd,hourkeysub:INSTD_LOGIC;

hour:outintegerrange0to23;

co:OUTSTD_LOGIC);

ENDcomponent;

componentday

PORT(elk,houro,daykeyadd,daykeysub:INSTD_LOGIC;

yue:inintegerrange1to31;

day:OUTintegerrange1to31;

co:OUTSTD_LOGIC);

ENDcomponent;

componentmonth

PORT(clk,dayo,monthkeyadd,monthkeysub,run:INSTD_LOGIC;

month:outintegerrange1to12;

yue:outintegerrange1to31;

co:OUTSTD_LOGIC);

ENDcomponent;

componentyear

PORT(clk,montho,yearkeyadd,yearkeysub:INSTD_LOGIC;

year:outintegerrange0to99;

run:OUTSTD_LOGIC);

ENDcomponent;

componentdisplay

PORT(

sec,cent:inintegerrange0to59;

hour:inintegerrange0to23;

day:inintegerrange1to31;

monthrinintegerrange1to12;

year:inintegerrange0to99;

cento,houro,elk,keyO,keyI,key2,key3:INSTD_LOGIC;

dis:OUTSTD_LOGIC_VECTOR(7DOWNTO0);

centkeyadd,centkeysub,hourkeyadd,hourkeysub,daykeyadd,daykeysu

b,monthkeyadd,monthkeysub:outstd_k)gic;--加减控制输出

yearkeyadd,yearkeysub:outstd_logic;

dis1en