实验例程2 1 led流水灯

2.1LED2LED2.1.1DONELED3，LED2.1.2USER2.1LED1ISE12.42LED2.1.1DONELED3，LED22.1.2USER2/2.1.3LED2.1.3LED3/1、板上LED电路图如下，FPGA输出高电平可以驱动LED亮，FPGA输出低电平LED图2.1.4板LED原理IO，方便对应查找，两组网络名都画到原理图上。图2.1.5板扩展口原理板原理图中查找P50，对应FPGA的IO为P119，D4对应P51，对应板上FPGA的IO微P120，依次类推2.1.6LED1、板上LED电路图如下，FPGA输出可以驱动LED亮，FPGA输出低电平LED图2.1.4板LED原理2IO电路图如下，IO_PxxFPGAIOP1X~P6x为扩展板对应IO，方便对应查找，两组网络名都画到原理图上。图2.1.5板扩展口原理3LEDP5.0~P5.7D3对应P502.1.4板原理图中查找P50，对应FPGA的IO为P119，D4对应P51，对应板上FPGAIO微P120，依次类推2.1.6LED4/"led[0]"LOC=P119;"led[1]"LOC=P120;"led[2]"LOC=P121;"led[3]"LOC=P123;"led[4]"LOC=P124;"led[5]"LOC=P126;"led[6]"LOC=P127;"led[7]"LOC=P131; 1sparametercount_1s //1sreg25:0]cnt_1s26'd0;计数器always@(posedgesystem_clk)cnt_1s<=elseif(cnt_1s<count_1s)cnt_1s<=cnt_1s+1'd1;cnt_1s<=同状态。状态机1s切换一个状态，20个状态为一个循环。reg[4:0]state=5'd0;state<=elseif(cnt_1s==count_1s&&state<state<=state+1'd1; elseif(cnt_1s==count_1s)state5'd0;7、LED状态显示，led<=8'b elsecase(state)led<=;led<=;led<=;led<=;led<=;led<=;NET"led[0]"LOC=P119;NET"led[1]"LOC=P120;NET"led[2]"LOC=P121;NET"led[3]"LOC=P123;NET"led[4]"LOC=P124;NET"led[5]"LOC=P126;NET"led[6]"LOC=P127;NET"led[7]"LOC=5、因为开发板系统时钟是50MHz，如果用这个时钟直接驱动LED进行流水灯，那么由 本实验采用的是计数器分频，设计一个1s钟的计数器，计数器加满后重新开始计parametercount_1s //1sreg25:0]cnt_1s26'd0计数器always@(posedgesystem_clk)cnt_1s<=elseif(cnt_1s<count_1s)cnt_1s<=cnt_1s+1'd1;cnt_1s<=6LED输出不同的电平信号，从而控制LED显示不1s切换一个状态，20个状态为一个循环。reg[4:0]state=5'd0;state<=elseif(cnt_1s==count_1s&&state<state<=state+1'd1; elseif(cnt_1s==count_1s)state5'd0;7LED状态显示，led<=else; led<= led<= led<= led<= led<= led<=;;;;;;////5/led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;defaultled<=;led<=;//D3led<=;//D4led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;led<=;defaultled<=;6/并生成Bit文件1、使用MiniUSB线将电脑与开发板连起来；使用USB方口线将电脑与XilinxUSB线14PIN灰排线将开发板与仿真器连起来。2WINDOWSISE12.4ISE3openProjectLED2.1.7LEDBit文件7/2.1.8bit2.1.9JTAG2.1.10ProjectImpact2.1.9JTAG6xc6slx9OK2.1.108/2.1.11bit2.1