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TimesNewRoman45A4掌握硬件描述语言——VerilogLED每按动一下按键，LEDLED计算机、QuatusII四、设计容（设计原理和方案、程序设计、仿真分析和适配拔河LED显16LEDLEDLED16LEDLEDLEDLED拔河LED显modulefpq(_10000HzOut,_25HzOut,_50MHzIn);input_50MHzIn;output_10000HzOut,_25HzOut;parameterwidth1=16,value1=2499;parameterwidth2=10,value2=499;reg_10000HzOut,_25HzOut;reg[width1-1:0]Count;reg[width2-1:0]Cnt;always(posedge if(Count==value1) //BinaryCounter(0~2499)Count<=15'd0;_10000HzOut<=~_10000HzOut;elseCount<=Count+always(posedge //100if(Cnt==value2) //BinaryCounter(0~99999)Cnt<=15'd0;_25HzOut<=~_25HzOut;elseCnt<=Cnt+1'b1;1，25hzmodulexiaodou(key1,key2,_25H,k1,input inputkey2; input_25H; //脉冲25Hzoutputk1;outputassign assignk2=(b1|b2|b3); rega1,a2,a3,b1,b2,b3;always(posedge_25H)2，led xin(k1,k2,rst,nrst,_25H,q,left,right);inputk1; input input inputnrst; input_25H; output[2:0] ledoutput[2:0]left; output[2:0]right; reg[2:0]q;regreg //regalways(negedgerstorposedge_25Hornegedgenrst)if(~rst)beginq=7;n=1;end //q,led回中点 n使能开elseif(~nrst)beginleft=0;right=0;end elseif(n) begin 2'b01: led2'b10:q=q- leddefault: 3'b000:beginn=0;left=left+1;end 3'b110:beginn=0;right=right+1;end//右+1分，n使能关 3，Led16moduleled(q,_50M,led);input[2:0]q;input_50M;output[7:0]led;reg[7:0]led;always(posedge_50M) 4，moduleshumaguan1(left,right,_10000H,segout,wx);input[2:0]left;input[2:0]right;input_10000H;output[6:0]segout; output[2:0]wx;reg[2:0]reg[6:0]reg[1:0]reg[3:0]seg_in;always(posedge_10000H) //leftwx+,计数输入=left,count2'd1:begin //-+,计数输入=8， //rihhtwx=right,conunt //gfedcba//