数字系统设计 - 触发器 Flip-Flops原理

触发器Flip-Flops

2ZDMC–Lec.#8RSQQ'RSQR'S'QQQ'S'R'MemorywithCross-coupledGatesCross-coupledNORgatesSimilartoinverterpair,withcapabilitytoforceoutputto0(reset=1)or1(set=1)

Cross-coupledNANDgatesSimilartoinverterpair,withcapabilitytoforceoutputto0(reset=0)or1(set=0)

复习NANDLatch3ZDMC–Lec.#8复习SettingtheLatch(FF)PulsingtheSETinputtothe0statewhen(a)Q=0priortoSETpulse;(b)Q=1priortoSETpulse.Notethat,inbothcases,QendsupHIGH.4ZDMC–Lec.#8复习ResettingtheLatch(FF)PulsingtheRESETinputtotheLOWstatewhen(a)Q=0priortoRESETpulse;(b)Q=1priortoRESETpulse.Ineachcase,QendsupLOW.5ZDMC–Lec.#8复习SummaryofNADNLatch(a)NANDlatch;(b)functiontable.6ZDMC–Lec.#8AlternateRepresentations(a)NANDlatchequivalentrepresentation;(b)simplifiedblocksymbol.7ZDMC–Lec.#8NORGateLatch(a)NORgatelatch(b)functiontable(c)simplifiedblocksymbol8ZDMC–Lec.#8Analyzeanddescribetheoperationofthecircuit9ZDMC–Lec.#810ZDMC–Lec.#8ObservedR-SLatchBehaviorVerydifficulttoobserveR-Slatchinthe1-1stateOneofRorSusuallychangesfirstAmbiguouslyreturnstostate0-1or1-0Aso-called"racecondition"Ornon-deterministictransitionSR=00SR=00QQ'

01QQ'

10QQ'

00SR=10SR=01SR=00SR=10SR=00SR=01SR=11SR=11SR=01SR=10SR=11复习11ZDMC–Lec.#8clockR'andS'changingstablechangingstablestableClocks(cont’d)ControllinganR-SlatchwithaclockCan'tletRandSchangewhileclockisactive(allowingRandStopass)OnlyhavehalfofclockperiodforsignalchangestopropagateSignalsmustbestablefortheotherhalfofclockperiodclock'S'Q'QR'RS复习12ZDMC–Lec.#8Master-SlaveStructureBreakflowbyalternatingclocks(likeanair-lock)UsepositiveclocktolatchinputsintooneR-SlatchUsenegativeclocktochangeoutputswithanotherR-SlatchViewpairasonebasicunitmaster-slaveflip-floptwiceasmuchlogicoutputchangesafewgatedelaysafterthefallingedgeofclockbutdoesnotaffectanycascadedflip-flopsmasterstageslavestagePP'CLKRSQQ'RSQQ'RS复习13ZDMC–Lec.#810gatesDFlip-FlopMakeSandRcomplementsofeachotherEliminates1scatchingproblemCan'tjustholdpreviousvalue(musthavenewvaluereadyeveryclockperiod)ValueofDjustbeforeclockgoeslowiswhatisstoredinflip-flopCanmakeR-Sflip-flopbyaddinglogictomakeD=S+R'QDQQ'masterstageslavestagePP'CLKRSQQ'RSQQ'复习14ZDMC–Lec.#7Set1s

catchSRCLKPP'QQ'ResetMaster

OutputsSlave

OutputsThe1sCatchingProblemInfirstR-Sstageofmaster-slaveFF0-1-0glitchonRorSwhileclockishigh"caught"bymasterstageLeadstoconstraintsonlogictobehazard-freemasterstageslavestagePP'CLKRSQQ'RSQQ'RS15ZDMC–Lec.#8QDClk=1RS0D’0D’DQ’negativeedge-triggeredD

flip-flop(D-FF)4-5gatedelaysmustrespectsetupandholdtime

constraintstosuccessfully

captureinputcharacteristicequation

Q(t+1)=DholdsD'whenclockgoeslowholdsDwhen

clockgoeslowEdge-TriggeredFlip-FlopsMoreefficientsolution:only6gatessensitivetoinputsonlynearedgeofclocksignal(notwhilehigh)16ZDMC–Lec.#8QDClk=0RSDD’D’D’Dwhenclockgoeshigh-to-lowdataislatchedwhenclockislowdataisheldEdge-TriggeredFlip-Flops(cont’d)Step-by-stepanalysisQnewDClk=0RSDD’D’D’DnewD

oldD17ZDMC–Lec.#8QDClk=1RSDD’D’D’DEdge-TriggeredFlip-Flops(cont’d)D=0,ClkHigh01000011HoldstateActasinverters18ZDMC–Lec.#80QDClk=1RSDD’D’D’DEdge-TriggeredFlip-Flops(cont’d)D=1,ClkHigh01000®

10®

101101®

01®

019ZDMC–Lec.#80100QDClk=0RSDD’D’D’DEdge-TriggeredFlip-Flops(cont’d)D=1,ClkLOW0®

11®

00010010®

1Actasinverters20ZDMC–Lec.#8positiveedge-triggeredFFnegativeedge-triggeredFFDCLKQposQpos'QnegQneg'100Edge-TriggeredFlip-Flops(cont’d)Positiveedge-triggeredInputssampledonrisingedge;outputschangeafterrisingedgeNegativeedge-triggeredflip-flopsInputssampledonfallingedge;outputschangeafterfallingedge21ZDMC–Lec.#8NegativeEdgeTriggerFFinVerilogmoduled_ff(q,q_bar,data,clk);inputdata,clk;outputq,q_bar;regq;assignq_bar=~q;always@(negedgeclk)beginq<=data;endendmodule22ZDMC–Lec.#8behavioristhesameunlessinputchangeswhiletheclockishighD QCLKpositive

edge-triggered

flip-flopD QGCLKtransparent

(level-sensitive)

latchDCLKQedgeQlatchComparisonofLatchesandFlip-Flops23ZDMC–Lec.#8Type

Wheninputsaresampled

Whenoutputisvalidunclocked always propagationdelayfrominputchange

latch level-sensitive clockhigh propagationdelayfrominputchange

latch (Tsu/Tharoundfalling orclockedge(whicheverislater)

edgeofclock)master-slave clockhigh propagationdelayfromfallingedge

flip-flop (Tsu/Tharoundfalling ofclock

edgeofclock)negative clockhi-to-lotransition propagationdelayfromfallingedge

edge-triggered (Tsu/Tharoundfalling ofclock

flip-flop edgeofclock)ComparisonofLatchesandFlip-Flops(cont’d)24ZDMC–Lec.#8本讲内容边沿触发器时序的基本概念Flip-Flop分类25ZDMC–Lec.#8TimingMethodologiesRulesforinterconnectingcomponentsandclocksGuaranteeproperoperationofsystemwhenstrictlyfollowedApproachdependsonbuildingblocksusedformemoryelementsFocusonsystemswithedge-triggeredflip-flopsFoundinprogrammablelogicdevicesManycustomintegratedcircuitsfocusonlevel-sensitivelatchesBasicrulesforcorrecttiming:(1)Correctinputs,withrespecttotime,areprovidedtotheflip-flops(2)Noflip-flopchangesstatemorethanonceperclockingevent26ZDMC–Lec.#8thereisatiming"window"

aroundtheclockingevent

duringwhichtheinputmust

remainstableandunchanged

inordertoberecognizedclockdatachangingstableinputclockTsuThclockdataDQDQTimingMethodologies(cont’d)Definitionoftermsclock:periodicevent,causesstateofmemoryelementtochange;canberisingorfallingedge,orhighorlowlevelsetuptime:minimumtimebeforetheclockingeventbywhichtheinputmustbestable(Tsu)holdtime:minimumtimeaftertheclockingeventuntilwhichtheinputmustremainstable(Th)27ZDMC–Lec.#8allmeasurementsaremadefromtheclockingeventthatis,

therisingedgeoftheclockTypicalTimingSpecificationsPositiveedge-triggeredDflip-flopSetupandholdtimesMinimumclockwidthPropagationdelays(lowtohigh,hightolow,maxandtypical)Th

5nsTw25nsTplh

25ns

13nsTphl

40ns

25nsTsu

20nsDCLKQTsu

20nsTh

5ns28ZDMC–Lec.#8INQ0Q1CLK100CascadingEdge-triggeredFlip-FlopsShiftregisterNewvaluegoesintofirststageWhilepreviousvalueoffirststagegoesintosecondstageConsidersetup/hold/propagationdelays(propmustbe>hold)CLKINQ0Q1DQDQOUT29ZDMC–Lec.#8timingconstraintsguaranteeproperoperationofcascadedcomponentsassumesinfinitelyfast

distributionoftheclockCascadingEdge-triggeredFlip-Flops(cont’d)WhythisworksPropagationdelaysexceedholdtimesClockwidthconstraintexceedssetuptimeThisguaranteesfollowingstagewilllatchcurrentvaluebeforeitchangestonewvalueTsu4nsTp3nsTh2nsInQ0Q1CLKTsu4nsTp3nsTh2ns30ZDMC–Lec.#8originalstate:IN=0,Q0=1,Q1=1duetoskew,nextstatebecomes:Q0=0,Q1=0,andnotQ0=0,Q1=1CLK1isadelayedversionofCLK0InQ0Q1CLK0CLK1100ClockSkewTheproblemCorrectbehaviorassumesnextstateofallstorageelements

determinedbyallstorageelementsatthesametimeDifficultinhigh-performancesystemsbecausetimeforclocktoarriveatflip-flopiscomparabletodelaysthroughlogic(andwillsoonbecomegreaterthanlogicdelay)Effectofskewoncascadedflip-flops:31ZDMC–Lec.#8触发器Flip-Flop分类逻辑功能分类RS锁存器JK触发器T触发器D触发器逻辑功能指按触发器的次态和现态及输入信号之间的逻辑关系.特性表特性方程状态转换图32ZDMC–Lec.#8RS锁存器特性方程Qn+1=S+R’QnRSLatch的状态转换图特性表/真值表01S=1,R=0S=0,R=1S=X,R=0S=0,R=XSRQnQn+1000000110100

01101001101111001110保持复位置位不定33ZDMC–Lec.#8JK触发器特性方程:Qn+1=JQn’+K’QnJKFF的状态转换图特性表/真值表01J=1,K=XJ=X,K=1J=X,K=0J=0,K=XJKQnQn+1000