《集成电路专业英语》全套教学课件

1IntroductiontoSemiconductorPartIIntegratedCircuitFundamentals-

SemiconductorPhysics

1IntroductiontoSemiconductor2EnergyBandsandChargeCarriersinSemiconductors3Diode4BipolarJunctionTransistors(BJTs)5Field-EffectTransistors(FETs)6SpecialSemiconductorDevices7AnalogIntegratedCircuits8DigitalIntegratedCircuits9EDATools10WaferFabrication11Fabrication12CMOSandFinFETTechnology13IntegratedCircuitPackaging14IntegratedCircuitTesting全套可编辑PPT课件IntroductiontoSemiconductorsPrimarymaterialsforIntegratedCircuits(ICs)anddevicesliketransistorsanddiodesEnableinformationprocessing,speed,efficiency,andpowercontrolAdvancedmaterialsincludeGaNandSiCforcutting-edgeapplicationsDefinition&ElectricalResistivitySemiconductorshaveelectricalpropertiesbetweeninsulatorsandconductorsResistivityrange:10^-4to10^8Ω-cm(e.g.,Silicon,Germanium)CriticalforcontrolledelectronflowinelectronicsClassificationofSemiconductorsElementalsemiconductorsfromGroupIVelementsCompoundsemiconductorsfromcombinationslikeGroupIII-VIntrinsic(pure)vsExtrinsic(doped)materialsElementalvs.CompoundMaterialsElemental:Silicon(Si)andGermanium(Ge)Compound:GaAs,GaPwithsuperioropticalandspeedpropertiesUsedinhigh-speedandoptoelectronicapplicationsAtomicStructureofSiliconSiliconhas4valenceelectronsformingcovalentbondsCreatesastablecrystallatticestructureAt0K,siliconbehavesasaperfectinsulatorThermalGeneration&CarrierMovementThermalenergybreakscovalentbondsatroomtemperatureGeneratesfreeelectronsandholesConductivityincreaseswithtemperatureIntrinsicCarrierConcentrationInintrinsicsilicon:n=p=ninidependsontemperatureandbandgapenergyForSiatroomtemperature:~1.5×10^10cm^-3IntroductiontoDopingIntrinsicsiliconhaslowandtemperature-sensitiveconductivityDopingintroducesimpuritiestocontrolconductivityDonorscreateN-type;AcceptorscreateP-typeExtrinsicSemiconductor:N-TypeDopedwithpentavalentelementslikePhosphorusExtraelectronbecomesfreeandincreasesconductivityElectronsaremajoritycarriersExtrinsicSemiconductor:P-TypeDopedwithtrivalentelementslikeBoronCreatesholesasmajoritycarriersKnownasP-type(positivetype)materialKeyTerminologyIntegratedCircuit:multiplecomponentsononechipBandgapEnergy:energytobreakcovalentbondsRecombination:electron-holeannihilationReview&ExercisesSemiconductorsbalanceconductivitybetweeninsulatorsandconductorsDopingcreatesN-typeandP-typematerialsExercises:resistivityrangeandintrinsicvsextrinsic2EnergyBandsandChargeCarriersinSemiconductorIntroductionElectricalconductivitycanbepreciselymanipulatedControlledbydoping,electricfields,andlightHighlysensitivetotemperatureandexternalstimuli163TheFormationofEnergyBandsIsolatedatomshavediscreteenergylevelsInsolids,atomicorbitalsoverlapandformenergybandsInnerorbitelectronsremainlargelyunaffectedKeyEnergyBandClassificationsValenceband:highestoccupiedenergybandConductionband:freeelectronsresponsibleforcurrentForbiddengapseparatesvalenceandconductionbandsMaterialClassificationbyBandGapInsulatorshavelargebandgapspreventingconductionSemiconductorshavesmallgaps(Si:1.1eV,Ge:0.72eV)ConductorshaveoverlappingbandsChargeCarrierDynamics:DriftCurrentDriftiscausedbyanappliedelectricfieldElectronsmoveoppositetothefield;holesmovewithitElectronmobilityis~2.5xholemobilityinsiliconMathematicsofDriftandResistivityDriftvelocityproportionaltoelectricfieldandmobilityCurrentdensitydependsoncarrierconcentrationandmobilityResistivityinverselyrelatedtocarriertransportChargeCarrierDynamics:DiffusionCurrentDiffusiondrivenbynon-uniformcarrierconcentrationCarriersmovefromhightolowconcentrationDiffusionconstantsdifferforelectronsandholesTheEinsteinRelationshipLinksdiffusionconstantandmobilityDefinedbythermalvoltageVT=kT/qAt300K,VT≈25.9mVSummaryofKeyTermsValenceelectronsoccupytheouteratomicshellHolesactaspositivechargecarriersBandgapdeterminesconductioncapability3DiodePartIIIntegratedCircuitFundamentals-SemiconductorDevicesIntroductiontoDiodesFundamentalsemiconductordevicesbasedonthePNjunctionFormedbyjoiningP-typeandN-typeregionsonasinglesubstrateProvideunidirectionalcurrentflowformanyapplicationsPNJunctionFormationP-typehashighholeconcentration;N-typehashighelectronconcentrationDiffusionandrecombinationoccurattheinterfaceIonizedatomsformthespacecharge(depletion)regionInternalElectricField&EquilibriumInternalelectricfieldformsfromN-regiontoP-regionDiffusionanddriftcurrentsopposeeachotherEquilibriumresultsinzeronetcurrentwithoutbiasBiasingConditions:Zero&ReverseBiasZerobias:noexternalvoltage,barrierpreventscurrentflowReversebiaswidensthedepletionregionOnlyaverysmallleakagecurrentflowsBiasingConditions:ForwardBiasForwardbiasreducesdepletionwidthAllowslargecurrentflowwithlowresistanceBarriervoltage:~0.7V(Si),~0.3V(Ge)IVCharacteristicsofaDiodeNon-linear,exponentialcurrent-voltagerelationshipKneepointmarksrapidcurrentincreaseHighreversevoltagecausesavalanchebreakdownSpecialDiodes:ZenerDiodesOperateinreversebreakdownatafixedZenervoltageHeavilydopedtocontrolbreakdownpreciselyWidelyusedforvoltageregulationSpecialDiodes:SchottkyDiodesFormedbyametal–semiconductorjunctionVeryfastswitchingandlowforwardvoltagedropUsedinhigh-speedandRFapplicationsOptoelectronics:LEDs&SolarCellsLEDsemitlightthroughelectroluminescenceSolarcellsconvertlightintoelectricalenergyKeyparametersincludeIscandVocSummaryofKeyTermsSubstrate:basematerialfordevicefabricationSpacechargeregion:depletionlayeratthejunctionMajoritycarriers:holesinP-type,electronsinN-type4BipolarJunctionTransistors(BJTs)IntroductiontoBipolarJunctionTransistors(BJTs)TransistorsaretheprimarybuildingblocksofmodernelectroniccircuitsBJTswerethefirsttransistorsdevelopedandarestillwidelyusedUsedforsignalamplificationandswitching;current-controlleddevicesBJTStructureandTypesThreeterminals:Base(B),Collector(C),andEmitter(E)Constructedfromthreedopedregionsformingtwop–njunctionsTwotypes:npnandpnptransistorsBasicOperationPrinciplesBase–EmittercurrentcontrolsCollectorcurrentCollectorandEmitterarenotinterchangeableduetoasymmetryOperationinvolvesbothmajorityandminoritycarriersBJTvs.MOSFET(FET)BJTiscurrent-controlled;MOSFETisvoltage-controlledBJTisbipolar;MOSFETisunipolarBJTsamplifycurrent;MOSFETscontrolcurrentviavoltageCircuitConfigurationsandVoltagesThreeconfigurations:Common-Base,Common-Emitter,Common-CollectorSupplyvoltages:VCCandVBBTerminalandjunctionvoltagesdefineoperationOperatingRegimesSaturation:maximumcollectorcurrent,bothjunctionsforwardbiasedCutoff:nobase-emitterconduction,zerocurrentUsedasON/OFFswitchindigitalapplicationsTechnicalGlossaryBipolarJunctionTransistor(BJT):双极结型晶体管FieldEffectTransistor(FET):场效应晶体管Common-Emitter,Saturation,Cutoff:keyoperatingterms5Field-EffectTransistors(FETs)IntroductiontoFETsVoltage-controlledunipolardevicesusingmajoritycarriersControlledbyanelectricfieldratherthaninputcurrentHighinputimpedance,lowpower,idealforICsJunctionFET(JFET)StructureThreeterminals:Gate,Drain,andSourceConstructedfromathinsemiconductorbar(SiorGaAs)N-channelandP-channeltypesKeyCharacteristicsofJFETsVeryhighinputimpedanceandlownoiseCurrentcarriedonlybymajoritycarriersTemperature-dependentcharacteristicsJFETOutputCharacteristicsIdvsVdsatconstantVgsOhmic,Saturation,Pinch-off,andBreakdownregionsDraincurrentcontrolledbygatevoltageJFETTransferCharacteristicsRelationshipbetweenIdandVgsatfixedVdsIddecreasesasVgsbecomesmorenegative(N-channel)DefinestransconductanceMOSFETStructure&OperationInsulated-gateFETwithoxidelayerExtremelyhighinputimpedanceChannelformswhenVGSexceedsthresholdvoltageMOSFETModesandScalingEnhancementanddepletionmodesExcellentscalabilityforVLSIDominantdeviceinCPUsandmemoryComplementaryMOS(CMOS)TechnologyUsesbothNMOSandPMOSdevicesVerylowstaticpowerconsumptionGlobalstandardforintegratedcircuitsSummaryofKeyTermsThresholdvoltagedefineschannelformationTransfercharacteristicsdescribegatecontrolGaAsusedasalternativeJFETmaterial6SpecialSemiconductorDevicesIntroductiontoSpecialSemiconductorsDesignedforhigh-stakesrequirementsbeyondbasicdevicesEnablepowercontrolandphotonicapplicationsEssentialtopowerelectronicsandoptoelectronicsThyristors–GateTurn-Off(GTO)Threeterminals:Anode,Cathode,andGateCanbeturnedONandOFFusinggatecontrolUsedininverters,choppers,andtractionsystemsTRIACs(TriodeACSwitch)BidirectionalconductionforACpowercontrolEquivalenttotwoSCRsinantiparallelTurnedoffwhencurrentcrosseszeroDIACs(DiodeforAlternatingCurrent)BidirectionaldiodewithoutagateterminalConductsafterreachingbreakovervoltageCommonlyusedtotriggerTRIACsPhotonicDevices–PhotodiodesConvertincidentlightintophotocurrentOftenusePINjunctionforbetterperformanceBandwidthaffectedbyjunctioncapacitanceSolarCells(PhotovoltaicEnergy)ConvertsunlightintoelectricalenergyBasedonp–njunctioncarrierseparationFuturetrendsincludeadvancedsiliconstructuresPowerDiodesDesignedforhighvoltageandcurrenthandlingUseP+–N−junctionstructuresUsedinrectifiersandprotectioncircuitsPowerTransistorsHigh-powerBJTscontrollargecurrentsSmallbasecurrentcontrolslargecollectorcurrentUsedinSMPS,converters,andinvertersTechnicalSummaryGTO:gate-controlledpowerswitchingTRIAC&DIAC:ACpowercontrolandtriggeringPhotodiodes&SolarCells:optoelectronicenergyconversion7AnalogIntegratedCircuitsPartIIIIntegratedCircuitDesignWhyAnalogICsMatterNotallfunctionscanberealizeddigitallyFront-endsignalconditioningisalwaysanalogHigh-speeddigitalsystemsrelyonanalogprinciplesAnalogvsDigitalProcessingAnalog:continuous-time,sensitivetonoiseanddistortionDigital:discretelevels(0/1),toleranttonoiseModernsystemscombinebothdomainsOperationalAmplifiers(Op-Amps)High-gainmulti-stageamplifiersDifferentialinput,single-endedoutputCorebuildingblockofanalogICdesignOp-AmpSymbolandTerminalsInverting(−)inputNon-inverting(+)inputOutputterminalPositiveandnegativesupplyrailsSimplifiedOp-AmpModelModeledasavoltage-controlledvoltagesourceVeryhighinputresistanceLowoutputresistanceLargeopen-loopgainOp-AmpKeyParametersInputoffsetvoltageInputbiascurrentOpen-loopgainOutputvoltageswingPARAMETERTESTCONDITIONSLF411ALF411UNITMINTYPMAXMINTYPMAXVOSInputOffsetVoltageRS=10kΩ,TA=25℃

0.30.5

0.82.0mVΔVOS/ΔTAverageTCofInputOffsetVoltageRS=10kΩ

7

7

μV/℃IOSInputOffsetCurrentVS=±15V(2)(3)Tj=25℃

25100

25100pATj=70℃

2

2nATj=125℃

25

25nAIBInputBiasCurrentVS=±15V(2)(3)Tj=25℃

50200

50200pATj=70℃

4

4nATj=125℃

50

50nARINInputResistanceTj=25℃

1012

1012

ΩAVOLLargeSignalVoltageGainVS=±15V,VO=±10V,RL=2k,TA=25℃50200

25200

V/mVOverTemperature25200

15200

V/mVVOOutputVoltageSwingVS=±15V,RL=2k±12±13.5

±12±13.5

VVCMInputCommon-ModeVoltageRange

±16+19.5

±11+14.5

V

-16.5

-11.5

VCMRRCommon-ModeRejectionRatioRS≤10k80100

70100

dBPSRRSupplyVoltageRejectionRatioSee(4)80100

70100

dBISSupplyCurrent

1.82.8

1.83.4mAOp-AmpACCharacteristicsSlewrateGain-bandwidthproduct(GBW)InputnoisevoltageandcurrentTotalharmonicdistortion(THD)PARAMETER(1)(2)TESTCONDITIONSLF411ALF411UNITMINTYPMAXMINTYPMAXSRSlewRateVS=±15V,TA=25℃1015

815

V/μsGBWGain-BandwidthProductVS=±15V,TA=25℃34

2.74

MHzenEquivalentInputNoiseVoltageTA=25℃,RS=100Ω,f=1kHz

25

25

nV/√HzinEquivalentInputNoiseCurrentTA=25℃,f=1kHz

0.01

0.01

pA/√HzTHDTotalHarmonicDistortionAV=+10,RL=10k,VO=20Vp-p,BW=20Hz-20kHz

<0.02%

<0.02%

VoltageReferencesProvidestable,accuratevoltagesCriticalforADCandDACaccuracyAccuracydirectlylimitssystemresolutionTypesofVoltageReferencesSeries(three-terminal)referencesShunt(two-terminal)referencesTrade-offsinaccuracy,current,andflexibilityDiode-BasedReferencesForward-biaseddiodereferencesZener/avalanchediodereferencesSimplebutlimitedaccuracyandnoiseperformanceBandgapVoltageReferencesBasedonsiliconbandgap(~1.205V)ExcellenttemperaturestabilityOperatesatlowsupplyvoltagesBrokawBandgapCellUsesΔVBEandVBEsummationTemperaturecoefficientminimizedFoundationofmodernprecisionreferencesAnalogFiltersFrequency-selectivesignalprocessingSuppressinterferenceandnoiseEssentialincommunicationsystemsFilterTypesLow-passfilter(LPF)High-passfilter(HPF)Band-passfilter(BPF)Band-stopfilter(BSF)FilterSpecificationsPassbandripple(Amax)Stopbandattenuation(Amin)CutofffrequenciesTransitionbandandselectivityDataConvertersOverviewInterfacebetweenanaloganddigitaldomainsDigital-to-AnalogConverters(DACs)Analog-to-DigitalConverters(ADCs)Digital-to-AnalogConverters(DACs)ConvertdigitalcodesintoanalogvoltagesorcurrentsResolutiondefinedbynumberofbitsAccuracydependsonreferenceandmatchingR-2RLadderDACUsesonlyRand2RresistorsExcellentmatchingpropertiesWidelyusedinICDACsModernDACFeaturesIntegratedvoltagereferenceOutputbufferamplifiersSerialandparalleldigitalinterfacesAnalog-to-DigitalConverters(ADCs)QuantizeanalogsignalsintodigitalcodesResolutionandsamplingratedefineperformanceKeyelementindataacquisitionsystemsADCFunctionalBlocksSample-and-holdcircuitQuantizerandencoderReferencevoltagesourceADCClockingandControlSamplingclockrequirementsvarybyarchitectureEnd-of-conversion(EOC)anddata-readysignalsCarefultimingrequiredforreliableoperationTrendsinDataConvertersLowersupplyvoltagesHigherresolutionandspeedDifferentialinputsforbetterSNRSummaryAnalogICsremainessentialinmodernelectronicsOp-amps,references,filters,andconvertersformthecoreUnderstandingfundamentalsiscriticalforsystemdesign8

DigitalIntegratedCircuitsIntroduction&Moore'sLawCoreConcept:Thefundamentalbuildingblocksofallmoderncomputingsystems.Builtfrommillionstobillionsofmicroscopictransistorsonasinglesemiconductorchip.TheirdevelopmenthashistoricallyfollowedMoore'sLaw:thenumberoftransistorsonachipdoublesapproximatelyeverytwoyears.Thisexponentialgrowthpowerseverythingfromsmartphonestomedicalequipment.DesignMethodology:Ahierarchicalapproach,startingfrombasiclogicgatesandbuildinguptocomplexdigitalsystems.TheFoundation:BooleanAlgebra&LogicLevelsBooleanAlgebra:Variablesandconstantscanonlyhavetwovalues:0or1.Thesevaluesrepresentlogiclevels,notnumericalvalues.LogicLevelsinPractice:Logic0(LOW):e.g.,0Vto0.8V;Logic1(HIGH):e.g.,2Vto5V.SynonymsforLogic0:False,Off,Low,No,OpenSwitch.SynonymsforLogic1:True,On,High,Yes,ClosedSwitch.BasicOperations:OR,AND,NOT.BasicLogicGates–TheORGateFunction:OutputisHIGH(1)ifanyinputisHIGH(1).BooleanExpression:X=A+B(XequalsAORB).Real-worldAnalogy:AnovenlightturnsoniftheswitchisONORthedoorisopened.BasicLogicGates–TheANDGateFunction:OutputisHIGH(1)onlyifallinputsareHIGH(1).BooleanExpression:X=A·BorX=AB(XequalsAANDB).Real-worldAnalogy:AclothesdryerrunsonlyifthetimerissetANDthedoorisclosed.BasicLogicGates–TheNOTGate(Inverter)Function:Performsinversionorcomplementationonasingleinput.BooleanExpression:X=Ā(XequalsNOTA).KeyProperty:Theoutputisalwaystheoppositeoftheinput.CombinationalCircuits:AnOverviewDefinition:Aninterconnectionoflogicgateswheretheoutputdependsonlyonthecurrentinputvalues.BlockDiagram:nInputVariables→CombinationalLogicCircuit→mOutputVariables.SpecificationMethods:TruthtablesandBooleanfunctions.Examples:Adders,Multiplexers,Decoders,Encoders.CombinationalBuildingBlock:TheHalfAdderPurpose:Addstwosingle-bitbinarynumbers(xandy).Outputs:S(Sum)andC(Carry).BooleanFunctions:S=x'y+xy'(x⊕y),C=xy.CombinationalBuildingBlock:TheFullAdderPurpose:Addsthreesingle-bitbinarynumbers(x,y,andcarry-inz).S=1whenanoddnumberofinputsare1.C=1whentwoorthreeinputsare1.Implementation:TwohalfaddersandoneORgate.CombinationalBuildingBlock:TheMultiplexer(MUX)Function:Adataselectorthatroutesoneofmanyinputlinestoasingleoutputline.Selectionisdeterminedbynselectionlines.Commontypesinclude2-to-1and4-to-1multiplexers.CombinationalBuildingBlock:TheDecoderFunction:Convertsann-bitbinaryinputcodeintoamaximumof2^nactiveoutputlines.OnlyoneoutputisHIGHforanyinputcombination.Usedinmemoryaddressdecodingandbinaryconversion.CombinationalBuildingBlock:TheEncoderFunction:Theinverseofadecoder.Convertsanactiveinputlineintoann-bitbinarycode.Priorityencodersresolvemultipleactiveinputconflicts.SequentialCircuits:AnOverviewOutputsdependoncurrentinputsandpaststate.Storageelementssuchasflip-flopsholdthecircuitstate.Thecircuittransitionsthroughstatesusingaclocksignal.SequentialBuildingBlock:Flip-FlopsSynchronousbistabledevicesthatchangestateataclockedge.Edge-triggered:sensitiveonlytorisingorfallingclockedges.InaDflip-flop,QtakesthevalueofDattheclockedge.SequentialBuildingBlock:LatchesLevel-sensitivebistablestoragedevices.Changestatewhiletheenablesignalisactive.S-Rlatchusescross-coupledNANDgatesandhasaninvalidstate.SequentialBuildingBlock:RegistersAregisterisagroupofnflip-flopsstoringann-bitword.Allflip-flopsshareacommonclock.Shiftregistersmovedataleftorrightfordataconversion.SequentialBuildingBlock:CountersAcountercyclesthroughapredefinedsequenceofstates.Themodulusdefinesthenumberofstatesinthecycle.Ann-bitbinarycountercountsfrom0to2^n−1.CounterTypes:Ripplevs.SynchronousRipplecountersaresimplebutslowduetocumulativepropagationdelay.Synchronouscountersuseacommonclockforallflip-flops.Synchronousdesignsarefasterbutrequiremorelogic.Summary&KeyTakeawaysDigitalICsarebuilthierarchicallyfromlogicgatestocomplexsystems.Combinationalcircuitsdependonlyoncurrentinputs.Sequentialcircuitsdependoninputsandstoredstate.Performanceinvolvestrade-offsbetweensimplicityandspeed.9EDAToolsIntroductiontoEDAToolsWhatareEDATools?SoftwaresuitesthatautomateICdesign,verification,andfabrication.Enablemanagementofcircuitswithbillionsoftransistors.Whyaretheyessential?Reducedesigntimeandhumanerror.Handlecomplexityatadvancednodes(7nm,5nm,etc.).Addresspower,performance,andmanufacturabilitychallenges.HistoricalEvolution:1960sschematiccapture;1980s–90sHDL&synthesis;TodayAI/MLandcloudintegration.TheRoleofEDAinModernICDesignEDAtoolsarethebackboneofmodernICdesign.Transformhowcircuitsaredesigned,simulated,laidout,andverified.EnableinnovationbyautomatingrepetitivetaskssuchasDRC,LVS,andtiminganalysis.CriticalforMoore’sLawcontinuationandsystem-on-chip(SoC)integration.AnalogICEDAFlowOverviewSchematicCapture–Drawcircuitusingsymbols.Simulation–Verifybehavior(DC,AC,transient).LayoutEditing–Physicalplacementandrouting.Verification–DRCandLVSchecks.Tools:CadenceVirtuoso,SpectreSimulator,Calibre.SchematicCaptureinCadenceVirtuosoCreateadesignlibraryattachedtoaPDK(e.g.,smic18mmrf).BuildcellssuchasaCMOSinverterusingNMOSandPMOS.NMOS:W=1μm,L=180nm;PMOS:W=2μm,L=180nm.Addpinsandpowersymbols(vdd,gnd).Generatesymbolviewforreuse.AnalogSimulationwithSpectre(ADE)LaunchAnalogDesignEnvironment(ADEL).SetupDCSweep:Vinfrom0Vto1.8V,plotVoutVTC.SetupTransientAnalysiswithpulseinputstimulus.Add1fFcapacitiveloadatoutput.PlotVinversusVouttoobserveswitchingbehavior.LayoutDesigninVirtuosoLayoutEditorCreatelayoutviewforinvertercell.UseGenerate→AllFromSourcetoauto-placedevices.DrawN-wellandP-substrateimplants.Addbodytieswith2×2M1_AAvias.RoutePolyforinputandMetal1foroutputandpower.LabelnetswithM1_text.Goal:Ensurelayoutmatchesschematicelectricallyandphysically.Post-LayoutVerificationwithCalibreDesignRuleCheck(DRC):Ensureslayoutcomplieswithmanufacturingrules.Examplerule:Metaldensity≥15%.Layoutvs.Schematic(LVS):Verifiestopologicalequivalence.SuccessfulLVSshowsmatchingnetlists.Bothchecksaremandatorybeforetape-out.DigitalICEDAFlowOverviewRTLDesignusingVHDLorVerilog.RTLSimulationforfunctionalverification.LogicSynthesistogate-levelnetlist.Gate-levelsimulationwithdelays.PlaceandRoutetogeneratephysicallayout.Tools:irun,DesignCompiler,Vivado/Xilinx.RTLDesign&SimulationWriteVHDLcodeformy_adderwithregisteredinputsandoutputs.Createtestbenchtoapplystimuliandverifyoutputs.Simulateusingirun.Viewwaveformsforinputsandoutputs.DebugusingScopeandObjectswindows.Changesignalradixforbetterinterpretation.LogicSynthesiswithDesignCompilerReadRTLfile(my_adder.vhd).Compileusingtargettechnologylibrary(e.g.,SMIC180nm).Generategate-levelnetlistwithareaandtimingreports.Viewsynthesizedschematiccomposedofstandardcells.SynthesisconvertsRTLintoanoptimizedgatenetwork.BehavioralSimulation(Post-SynthesisOptional)Addsimulationsourcesuchasmult_and_add_tb.v.SettestbenchasTopModule.Runbehavioralsimulation.Analyzewaveformsforcorrectnessandtiming.KeyEDATerminologySchematicCapture:Graphicalcircuitentry.Netlist:Connectivitydescription.PDK:ProcessDesignKitwithmodelsandrules.DRC:DesignRuleChecking.LVS:LayoutVersusSchematic.RTL:RegisterTransferLevel.Synthesis:RTLtogate-levelconversion.Place&Route:Physicalimplementation.SummaryAnalogEDAfocusesonprecision,devicephysics,andmanuallayout.DigitalEDAishighlyautomatedanddrivenbyHDLandstandardcells.Verificationismandatoryinbothanaloganddigitalflows.EDAenablesmodernelectronicsfromsmartphonestoAIchips.WithoutEDA,advancedICswouldbeimpossibletodesign.10WaferFabrication:TheFoundationofIntegratedCircuitManufacturingPartⅣIntegratedCircuitManufacturingProcessIntroduction:TheHeartofMicroelectronicsSemiconductorwaferfabricationisthefundamentalprocessinmicroelectronics.Itservesasthecornerstoneofmodernintegratedcircuit(IC)production.Fromrawmaterialstopolishedsiliconwafers:properties,purification,crystalgrowth,andwaferprocessing.WhySilicon？Abundant&cheap:derivedfromsilicondioxide(SiO₂)insandandquartz.Idealsemiconductorwithcontrollableconductivityandexcellentdopingcontrol.Formsasuperiornativeoxide(SiO₂)thatisstable,high-quality,andpreciselycontrollable.Materialstability:durableandnon-toxiccomparedwithGaAs;mustbeultra-puresinglecrystal.OtherFormsofSiliconSingle-CrystalSilicon:perfectlattice;foundationforalladvancedICwafers.PolycrystallineSilicon:manysmallcrystals;usedforgates,maskinglayers,andinterconnects.AmorphousSilicon:disorderedstructure;mainlyforsolarcellsanddisplays,notmainstreamICs.Step1:ProductionofRaw(Metallurgical-Grade)SiliconSourcematerial:Quartzite(SiO₂).Carbothermicreductioninanarcfurnaceat~1460°C.Reaction:SiO₂+2C→Si+2CO.Output:Metallurgical-GradeSilicon(98–99%purity),unsuitablefordirectICuse.Step2:PurificationtoElectronicGradeGoal:Electronic-GradeSiliconwith99.999999999%purity.Keyintermediate:Trichlorosilane(SiHCl₃).Multi-stepprocess:grinding,HClreaction,distillation,andpurification.Step3:DepositionofElectronic-GradeSilicon(EGS)ChemicalVaporDeposition(CVD)inaSiemensreactor.Reaction:SiHCl₃+H₂→Si+3HClat~1100°C.Producesultra-purepolycrystallinesiliconrodsforcrystalgrowth.SingleCrystalGrowth–Czochralski(CZ)MethodDominantmethodforover90%ofsiliconwafers.MeltedEGSinquartzcruciblewithaseedcrystalpulledupwardwhilerotating.Produceslargecylindricalsingle-crystalingotswithcontrolleddiameter.CZMethod:ProsandConsAdvantages:lowercostandverylargewaferdiameters(300mm+).Disadvantages:oxygencontaminationfromcrucible.Dopantconcentrationgradientalongingotlength.SingleCrystalGrowth–Float-Zone(FZ)MethodUsedforhigh-purityapplicationssuchaspowerdevices.Localizedmoltenzonepassesalongapolycrystallinerod.Nocruciblecontact,resultinginextremelypuresinglecrystals.FZMethod:ProsandConsAdvantages:extremelyhighpurityanduniformresistivity.Disadvantages:highercostanddifficultygrowinglargediameters.Dopingachievedviagasesinthegrowthchamber.FromIngottoWafer:InitialProcessingIngotisgroundtoprecise,uniformdiameter.Orientationflatsindicatecrystalorientationanddopingtype.Notchesreplaceflatsforwafers≥200mmtosavesurfacearea.WaferFabricationProcessFlowSawingLappingBeveling(EdgeRounding)EtchingPolishingStep1:SawingSlicesingotintothinwafers.Modernmulti-wiresawusesthinwiresandslurry.Cutshundredsofwaferssimultaneouslywithreducedkerfloss.Step2:Lapping&Step3:BevelingLappingremovessawdamageandimprovesflatness.Bevelinground