智力抢答器的设计和分析专家讲座

第3章智力抢答器设计与分析3.1系统设计要求

3.2系统设计方案

3.3主要VHDL源程序3.4系统仿真/硬件验证3.5设计技巧分析3.6系统扩展思绪

第1页3.1系统设计要求在许多比赛活动中，为了准确、公正、直观地判断出第一抢答者，通常设置一台抢答器，经过数显、灯光及音响等各种伎俩指示出第一抢答者。同时，还能够设置计分、犯规及奖惩计录等各种功效。本设计详细要求是：第2页(1)设计制作一个可容纳四组参赛者数字智力抢答器，每组设置一个抢答按钮供抢答者使用。(2)电路含有第一抢答信号判别和锁存功效。(3)设置计分电路。(4)设置犯规电路。第3页3.2系统设计方案依据系统设计要求可知，系统输入信号有：各组抢答按钮A、B、C、D，系统清零信号CLR，系统时钟信号CLK，计分复位端RST，加分按钮端ADD，计时预置控制端LDN，计时使能端EN，计时预置数据调整按钮TA、TB；系统输出信号有：四个组抢答成功是否指示灯控制信号输出口LEDA、LEDB、LEDC、LEDD，四个组抢答时计时数码显示控制信号若干，抢答成功组别显示控制信号若干，各组计分动态显示控制信号若干。第4页依据以上分析，我们可将整个系统分为三个主要模块：抢答判别模块QDJB；抢答计时模块JSQ；抢答计分模块JFQ。对于需显示信息，需增加或外接译码器，进行显示译码。考虑到FPGA/CPLD可用接口及普通EDA试验开发系统提供输出显示资源限制，这里我们将组别显示和计时显示译码器内设，而将各组计分显示译码器外接。整个系统组成框图如图3.1所表示。第5页图3.1智力抢答器组成框图第6页3.3主要VHDL源程序3.3.1抢答判别电路QDJBVHDL源程序--QDJB.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYQDJBISPORT(CLR:INSTD_LOGIC;A,B,C,D:INSTD_LOGIC;A1,B1,C1,D1:OUTSTD_LOGIC;STATES:OUTSTD_LOGIC_VECTOR(3DOWNTO0));第7页ENDENTITYQDJB;ARCHITECTUREARTOFQDJBISCONSTANTW1:STD_LOGIC_VECTOR:="0001";CONSTANTW2:STD_LOGIC_VECTOR:="0010";CONSTANTW3:STD_LOGIC_VECTOR:="0100";CONSTANTW4:STD_LOGIC_VECTOR:="1000";BEGINPROCESS(CLR,A,B,C,D)ISBEGIN第8页IFCLR='1'THENSTATES<="0000";ELSIF(A='1'ANDB='0'ANDC='0'ANDD='0')THENA1<='1';B1<='0';C1<='0';D1<='0';STATES<=W1;ELSIF(A='0'ANDB='1'ANDC='0'ANDD='0')THENA1<='0';B1<='1';C1<='0';D1<='0';STATES<=W2;ELSIF(A='0'ANDB='0'ANDC='1'ANDD='0')THENA1<='1';B1<='0';C1<='1';D1<='0';STATES<=W3;ELSIF(A='0'ANDB='0'ANDC='0'ANDD='1')THENA1<='0';B1<='0';C1<='0';D1<='1';STATES<=W4;ENDIF;ENDPROCESS;ENDARCHITECTUREART;第9页3.3.2计分器电路JFQVHDL源程序--JFQ.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYJFQISPORT(RST:INSTD_LOGIC;ADD:INSTD_LOGIC;CHOS:INSTD_LOGIC_VECTOR(3DOWNTO0);AA2,AA1,AA0,BB2,BB1,BB0:OUTSTD_LOGIC_VECTOR(3DOWNTO0);第10页CC2,CC1,CC0,DD2,DD1,DD0:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDENTITYJFQ;ARCHITECTUREARTOFJFQISBEGINPROCESS(RST,ADD,CHOS)ISVARIABLEPOINTS_A2,POINTS_A1:STD_LOGIC_VECTOR(3DOWNTO0);VARIABLEPOINTS_B2,POINTS_B1:STD_LOGIC_VECTOR(3DOWNTO0);VARIABLEPOINTS_C2,POINTS_C1:STD_LOGIC_VECTOR(3DOWNTO0);VARIABLEPOINTS_D2,POINTS_D1:STD_LOGIC_VECTOR(3DOWNTO0);第11页BEGINIF(ADD'EVENTANDADD='1')THENIFRST='1'THENPOINTS_A2:="0001";POINTS_A1:="0000";POINTS_B2:="0001";POINTS_B1:="0000";POINTS_C2:="0001";POINTS_C1:="0000";POINTS_D2:="0001";POINTS_D1:="0000";ELSIFCHOS="0001"THEN第12页IFPOINTS_A1="1001"THENPOINTS_A1:="0000";IFPOINTS_A2="1001"THENPOINTS_A2:="0000";ELSEPOINTS_A2:=POINTS_A2+'1';ENDIF;ELSEPOINTS_A1:=POINTS_A1+'1';ENDIF;ELSIFCHOS="0010"THEN第13页IFPOINTS_B1="1001"THENPOINTS_B1:="0000";IFPOINTS_B2="1001"THENPOINTS_B2:="0000";ELSEPOINTS_B2:=POINTS_B2+'1';ENDIF;ELSEPOINTS_B1:=POINTS_B1+'1';ENDIF;第14页ELSIFCHOS="0100"THENIFPOINTS_C1="1001"THENPOINTS_C1:="0000";IFPOINTS_C2="1001"THENPOINTS_C2:="0000";ELSEPOINTS_C2:=POINTS_C2+'1';ENDIF;ELSEPOINTS_C1:=POINTS_C1+'1';ENDIF;第15页ELSIFCHOS="1000"THENIFPOINTS_D1="1001"THENPOINTS_D1:="0000";IFPOINTS_D2="1001"THENPOINTS_D2:="0000";ELSEPOINTS_D2:=POINTS_D2+'1';ENDIF;ELSEPOINTS_D1:=POINTS_D1+'1';第16页ENDIF;ENDIF;ENDIF;AA2<=POINTS_A2;AA1<=POINTS_A1;AA0<="0000";BB2<=POINTS_B2;BB1<=POINTS_B1;BB0<="0000";CC2<=POINTS_C2;CC1<=POINTS_C1;CC0<="0000";DD2<=POINTS_D2;DD1<=POINTS_D1;DD0<="0000";ENDPROCESS;ENDARCHITECTUREART;第17页3.3.3计时器电路JSQVHDL源程序--JSQ.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYJSQISPORT(CLR,LDN,EN,CLK:INSTD_LOGIC;TA,TB:INSTD_LOGIC;QA:OUTSTD_LOGIC_VECTOR(3DOWNTO0);QB:OUTSTD_LOGIC_VECTOR(3DOWNTO0));第18页ENDENTITYJSQ;ARCHITECTUREARTOFJSQISSIGNALDA:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALDB:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(TA,TB,CLR)ISBEGINIFCLR='1'THENDA<="0000";DB<="0000";ELSE第19页IFTA='1'THENDA<=DA+'1';ENDIF;IFTB='1'THENDB<=DB+'1';ENDIF;ENDIF;ENDPROCESS;PROCESS(CLK)ISVARIABLETMPA:STD_LOGIC_VECTOR(3DOWNTO0);VARIABLETMPB:STD_LOGIC_VECTOR(3DOWNTO0);第20页BEGINIFCLR='1'THENTMPA:="0000";TMPB:="0110";ELSIFCLK'EVENTANDCLK='1'THENIFLDN='1'THENTMPA:=DA;TMPB:=DB;ELSIFEN='1'THENIFTMPA="0000"THENTMPA:="1001";IFTMPB="0000"THENTMPB:="0110";ELSETMPB:=TMPB-1;第21页ENDIF;ELSETMPA:=TMPA-1;ENDIF;ENDIF;ENDIF;QA<=TMPA;QB<=TMPB;ENDPROCESS;ENDARCHITECTUREART;第22页3.3.4译码器电路YMQVHDL源程序--YMQ.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYYMQISPORT(AIN4:INSTD_LOGIC_VECTOR(3DOWNTO0);DOUT7:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDYMQ;ARCHITECTUREARTOFYMQIS第23页BEGINPROCESS(AIN4)BEGINCASEAIN4ISWHEN"0000"=>DOUT7<="0111111"; --0WHEN"0001"=>DOUT7<="0000110"; --1WHEN"0010"=>DOUT7<="1011011"; --2WHEN"0011"=>DOUT7<="1001111"; --3WHEN"0100"=>DOUT7<="1100110"; --4WHEN"0101"=>DOUT7<="1101101"; --5WHEN"0110"=>DOUT7<="1111101"; --6第24页WHEN"0111"=>DOUT7<="0000111"; --7WHEN"1000"=>DOUT7<="1111111"; --8WHEN"1001"=>DOUT7<="1101111"; --9WHENOTHERS=>D