嵌入式硬件基础南京大学软件学院

EmbeddedHardwareFoundationContentCPUBusMemoryI/ODesign,developanddebug1.CPUI/OprogrammingBusy/waitInterrupt-drivenSupervisormode,exceptions,trapsCo-processorMemorySystemCacheMemorymanagementPerformanceandpowerconsumptionI/OdevicesUsuallyincludessomenon-digitalcomponent.TypicaldigitalinterfacetoCPU:CPUstatusregdataregmechanismApplication:8251UARTUniversalasynchronousreceivertransmitter(UART):providesserialcommunication.8251functionsareintegratedintostandardPCinterfacechip.Allowsmanycommunicationparameterstobeprogrammed.8251CPUinterfaceCPU8251status(8bit)data(8bit)serialportxmit/rcvProgrammingI/OTwotypesofinstructionscansupportI/O:special-purposeI/Oinstructions;memory-mappedload/storeinstructions.Intelx86providesin,outinstructions.MostotherCPUsusememory-mappedI/O.I/Oinstructionsdonotprecludememory-mappedI/O.ARMmemory-mappedI/ODefinelocationfordevice:DEV1EQU0x1000Read/writecode:LDRr1,#DEV1;setupdeviceaddressLDRr0,[r1];readDEV1LDRr0,#8;setupvaluetowriteSTRr0,[r1];writevaluetodevicepeekandpoke(UsingC)intpeek(char*location){ return*location;}voidpoke(char*location,charnewval){ (*location)=newval;}Busy/waitoutputSimultaneousbusy/waitinputandoutputwhile(TRUE){ /*read*/ while(peek(IN_STATUS)!=0); achar=(char)peek(IN_DATA); /*write*/ while(peek(OUT_STATUS)!=0); poke(OUT_DATA,achar);}InterruptI/OInterruptinterfaceCPUstatusregdataregmechanismPCintrrequestintrackdata/addressIRInterruptbehaviorBasedonsubroutinecallmechanism.Interruptforcesnextinstructiontobeasubroutinecalltoapredeterminedlocation.Returnaddressissavedtoresumeexecutingforegroundprogram.InterruptphysicalinterfaceCPUanddeviceareconnectedbyCPUbus.CPUanddevicehandshake:deviceassertsinterruptrequest;CPUassertsinterruptacknowledgewhenitcanhandletheinterrupt.Example:interrupt-driveninputandoutputvoidinput_handler();voidoutput_handler();main(){ while(TRUE){ if(gotchar){ while(peek(OUT_STATUS)!=0); poke(OUT_DATA,achar); gotchar=FALSE; } }}Example:characterI/Ohandlersvoidinput_handler(){ achar=peek(IN_DATA); gotchar=TRUE; poke(IN_STATUS,0);}voidoutput_handler(){}Example:interruptI/OwithbuffersQueueforcharacters:headtailheadtailaBuffer-basedinputhandlervoidinput_handler(){ charachar; if(full_buffer()) error=1; else{ achar=peek(IN_DATA); add_char(achar); } if(nchars==1){ poke(OUT_DATA,remove_char(); poke(OUT_STATUS,1);} }}Buffer-basedoutputhandlervoidoutput_handler(){ if(!empty_buffer()){poke(OUT_DATA,remove_char());/*sendcharacter*/poke(OUT_STATUS,1);/*turndeviceon*/ }}PrioritiesandvectorsTwomechanismsallowustomakeinterruptsmorespecific:PrioritiesdeterminewhatinterruptgetsCPUfirst.Vectorsdeterminewhatcodeiscalledforeachtypeofinterrupt.Mechanismsareorthogonal:mostCPUsprovideboth.PrioritizedinterruptsCPUdevice1device2devicenL1L2..LninterruptacknowledgeInterruptprioritizationMasking:interruptwithprioritylowerthancurrentpriorityisnotrecognizeduntilpendinginterruptiscomplete.Non-maskableinterrupt(NMI):highest-priority,nevermasked.Oftenusedforpower-down.InterruptvectorsAllowdifferentdevicestobehandledbydifferentcode.Interruptvectortable:handler0handler1handler2handler3InterruptvectortableheadInterruptvectoracquisitionCPUdeviceinterruputrequestinterruputack.vectorInterruptvectoracquisition:CPU:devicereceiverequestreceiveackreceivevectorInterruptsequenceCPUcheckspendinginterruptrequestsandacknowledgestheoneofhighestpriority.Devicereceivesacknowledgementandsendsvector.CPUlocatesthehandlerusingvectorasindexofinterrupttableandcallsthehandler.Softwareprocessesrequest.CPUrestoresstatetoforegroundprogram.SourcesofinterruptoverheadHandlerexecutiontime.Interruptmechanismoverhead.Registersave/restore.Pipeline-relatedpenalties.Cache-relatedpenalties.ARMinterruptsARM7supportstwotypesofinterrupts:Fastinterruptrequests(FIQs).Interruptrequests(IRQs).Interrupttablestartsatlocation0.ARMinterruptprocedureCPUactions:SavePC.CopyCPSRtoSPSR.ForcebitsinCPSRtorecordinterrupt.ForcePCtovector.Handlerresponsibilities:RestoreproperPC.RestoreCPSRfromSPSR.Clearinterruptdisableflags.ExceptionandTrapException:internallydetectederror.Exceptionsaresynchronouswithinstructionsbutunpredictable.Buildexceptionmechanismontopofinterruptmechanism.Exceptionsareusuallyprioritizedandvectorized.Trap(softwareinterrupt)anexceptiongeneratedbyaninstruction.Callsupervisormode.SupervisormodeMaywanttoprovideprotectivebarriersbetweenprograms.Avoidmemorycorruption.Needsupervisormodetomanagethevariousprograms.ARMCPUmodes处理器模式

描述用户模式(User,usr)正常程序执行的模式快速中断模式(FIQ,fiq)用于高速数据传输和通道处理外部中断模式(IRQ,irq)用于通常的中断处理管理模式(Supervisor,svc)供操作系统使用的一种保护模式数据访问中止模式(Abort,abt)用于虚拟存储及存储保护未定义指令中止模式(Undefined,und)用于支持通过软件仿真硬件的协处理器系统模式用于运行特权级的操作系统任务异常模式ARMCPUmodes(cont’d)SWI(Softwareinterrupt)指令格式SWI{<条件码>}immed_24SWI指令用来执行系统调用，处理器进入管理模式，CPSR保存到管理模式的SPSR中，并从地址0x08开始执行指令。<immed_24>由系统所解释。Co-processorCo-processor:addedfunctionunitthatiscalledbyinstruction.Floating-pointunitsareoftenstructuredasco-processors.ARMallowsupto16designer-selectedco-processors.Floating-pointco-processorusesunits1and2.MemorySystemCacheMemoryManagementUnitCacheSmallamountoffastmemorySitsbetweennormalmainmemoryandCPUMaybelocatedonCPUchipormoduleCacheoperation-overviewCPUrequestscontentsofmemorylocationCheckcacheforthisdataIfpresent,getfromcache(fast)Ifnotpresent,readrequiredblockfrommainmemorytocacheThendeliverfromcachetoCPUCacheincludestagstoidentifywhichblockofmainmemoryisineachcacheslotCacheoperationManymainmemorylocationsaremappedontoonecacheentry.Mayhavecachesfor:instructions;data;data+instructions(unified).Memoryaccesstimeisnolongerdeterministic.CacheorganizationsDirect-mapped:eachmemorylocationmapsontoexactlyonecacheentry.Fully-associative:anymemorylocationcanbestoredanywhereinthecache(almostneverimplemented).N-wayset-associative:eachmemorylocationcangointooneofnsets.ExampleCacheof64kByteCacheblockof4bytesi.e.cacheis16k(214)linesof4bytes16MBytesmainmemory24bitaddress(224=16M)222

blocks;28blockswillbemappedintoonecachelineontheaverageDirect-mappedcacheEachblockofmainmemorymapstoonlyonecachelinei.e.ifablockisincache,itmustbeinonespecificplaceAddressisintwopartsLeastSignificantwbitsidentifyuniquewordMostSignificantsbitsspecifyonememoryblockTheMSBsaresplitintoacachelinefieldrandatagofs-r(mostsignificant)DirectMapping

AddressStructureTags-rLineorSlotrWordw8142Direct-mappedcachevalid=tagindexoffsethitvaluetagdata10xabcdbytebytebyte...bytecacheblockFully-associativecacheSet-associativecacheWriteoperationsWrite-through:immediatelycopywritetomainmemory.Write-back:writetomainmemoryonlywhenlocationisremovedfromcache.MemorymanagementunitsMemorymanagementunit(MMU)translatesaddresses:CPUmainmemorymemorymanagementunitlogicaladdressphysicaladdressMemorymanagementtasksAllowsprogramstomoveinphysicalmemoryduringexecution.Allowsvirtualmemory:memoryimageskeptinsecondarystorage;imagesreturnedtomainmemoryondemandduringexecution.Pagefault:requestforlocationnotresidentinmemory.AddresstranslationRequiressomesortofregister/tabletoallowarbitrarymappingsoflogicaltophysicaladdresses.Twobasicschemes:segmented;paged.Segmentationandpagingcanbecombined(x86).Segmentsandpagesmemorysegment1segment2page1page2Segmentaddresstranslationsegmentbaseaddresslogicaladdressrangecheckphysicaladdress+rangeerrorsegmentlowerboundsegmentupperboundPageaddresstranslationpageoffsetpageoffsetpageibaseconcatenatePagetableorganizationsflattreepagedescriptorpagedescriptorCachingaddresstranslationsLargetranslationtablesrequiremainmemoryaccess.TLB:cacheforaddresstranslation.Typicallysmall.ARMmemorymanagementMemoryregiontypes:section:1Mbyteblock;largepage:64kbytes;smallpage:4kbytes.Anaddressismarkedassection-mappedormapped.Two-leveltranslationscheme.CPUper