西工大FPGA实验报告二

1、西北工业大学硬件描述语言语与FPGA实验报告学 院：学号：姓名：专 业：实验时间：实验地点：指导教师：西北工业大学20 年 月利用状态机实现比较复杂的接口设计一、实验目的及要求1.学习运用由状态机控制的逻辑开关，设计出一个比较复杂的接口逻辑； 2.在复杂设计中使用任务(task)结构，以提高程序的可读性；3.加深对可综合风格模块的认识。二、实验设备（环境）及要求预装了开发工具synplify、ModelSimSE的PC机。三、实验内容与步骤内容：利用状态机实现一个比较复杂的接口设计。步骤：1建立工程并编写模块源码；2编写测试模块并思考状态机是如何实现复杂的接口设计的；3布局布线并仿真；4记录数

2、据并完成实验报告。四、实验代码module writing(reset,clk,address,data,sda,ack); input reset, clk; input7:0 data, address; inout sda; output ack; reg link_write; reg3:0 state; reg4:0 sh8out_state; reg7:0 sh8out_buf; reg finish_F; reg ack; parameter idle=0,addr_write=1,data_write=2,stop_ack=3; parameter bit0=1,bit1=2,

3、bit2=3,bit3=4,bit4=5,bit5=6,bit6=7,bit7=8; assign sda=link_write ? sh8out_buf7: 1bz; always (posedge clk) begin if(!reset) begin link_write =0; state =idle; finish_F =0; sh8out_state =idle; ack =0; sh8out_buf =0; end else case(state) idle: begin link_write =0; finish_F =0; sh8out_state=idle; ack =0;

4、 sh8out_buf =address; state =addr_write; end addr_write: begin if(finish_F=0) begin shift8_out; end else begin sh8out_state = idle; sh8out_buf = data; state=data_write; finish_F=0; end end data_write: begin if(finish_F=0) begin shift8_out; end else begin link_write=0; state= stop_ack; finish_F=0; ac

5、k=1; end end stop_ack: begin ack=0; state=idle; end endcase end task shift8_out; begin case(sh8out_state) idle: begin link_write=1; sh8out_state=bit7; end bit7: begin link_write=1; sh8out_state=bit6; sh8out_buf=sh8out_buf1; end bit6: begin sh8out_state=bit5; sh8out_buf=sh8out_buf1; end bit5: begin s

6、h8out_state=bit4; sh8out_buf=sh8out_buf1; end bit4: begin sh8out_state=bit3; sh8out_buf=sh8out_buf1; end bit3: begin sh8out_state=bit2; sh8out_buf=sh8out_buf1; end bit2: begin sh8out_state=bit1; sh8out_buf=sh8out_buf1; end bit1: begin sh8out_state=bit0; sh8out_buf=sh8out_buf1; end bit0: begin link_w

7、rite=0; finish_F=1; end endcase end endtask endmodule/测试代码：timescale 1ns/100psdefine clk_cycle 50module writingTop; reg reset,clk; reg7:0data,address; wire ack,sda; always #clk_cycle clk =clk; initial begin clk=0; reset=1; data=0; address=0; #(2*clk_cycle) reset=0; #(2*clk_cycle) reset=1; #(100*clk_cycle) $stop; end always(posedge ack) begin data=data+1; address=address+1; end writing writing(.reset(