主板信号量测.ppt

1、Timing Analysis & Signal Simulation on PC Systems,By Pierre Lee at ARIMA 4/16/2002,Hold,Common Clock Data Transfer,D0 D1 D2,D0 D1 D2,Clock Driver,Driving,Receiving,Tco,Flight Time,Setup,1,2,3,4,Defining Tco,Din,Clock,OutputBuffer,InternalLogic,RL = 50 W,Clock rises t = 0,Vmeas,Tco,Load for Tco measu

2、rement (from databook),Tco = time from clock rise to Vmeas into test load,Components of Tco,Din,Clock,OutputBuffer,InternalLogic,RL = 50 W,Clock rises t = 0,Vmeas,Tco,Internal delay = from clock rise to the point where the output begins to switch,External (buffer) delay = howlong the buffer takes to

3、 drive thereference load to Vmeas,For Signal Integrity Purposes .,Its all in the Math .,Driving,Receiving,Tco,Flight Time,1,2,3,4,?,t = 0,Clock Jitter,Clock Driver,Clock Jitter occurs when the clock period varies from one period to the next Usually caused by PLL instability in the clock driver Jitte

4、r increases / decreases the clock period, decreasing the effective clock cycle,Clock Skew,D0 D1 D2,Clock Driver,D0 D1 D2,t = 0,t = 1,t = 2,Occurs when different devices see the clock transition at different times Increases / decreases the apparent clock cycle. Depending on which devices are driving

5、/ receiving Reduces the effective clock cycle,Bus Clock Cycle Budgeting,For each Driver Receiver path: Tflightmax Receiver(Hold) - Driver(Tcomin) + Skew + Crosstalk,Common Clock Bus Example,Intel Pentium-Pro reference design Processor/Chipset Bus (GTL+, 66 MHz) Intel GTL+ Design Guidelines,Defining

6、Device Timing,Timings taken from “AC (dynamic) Specifications” sections of Intel datasheets Most datasheets available via WWW Important parameters Clock Data Valid for GTL+ Bus Setup / Hold requirements for GTL+ signals PLL Jitter (if specd),Pentium Pro,440FX (timings from 440LX),Determining Flight

7、Times,Tflightmax = 4.50 ns Tflightmin = 0.45 ns,Signal Wave Propagation,Flight time t1 = L/c,c 6.5 in/ns Tflightmax = 4.50 ns Tflightmin = 0.45 ns 29in L 3in,Risk,Ohms law ?,i = (va-vb) / Rtrace,i when Rtrace 0,Model of transmission line,Signal Wave Propagation,Flight time t1 = L/c,Impedance Change,

8、Layer change Reference plane crossing Trace splitting Series component Connector Pull high & pull down,Impedance Change,Layer change,Reference plane crossing,Trace splitting,Series component,Connector,Pull high,Schematics vs. Layout,Microstrip Section,Zo = f( w, h, t, er),Zo = Characteristic impedan

9、ce (W) w = Width of trace (mils) t = Thickness of trace (mils) h = Thickness of dielectric layer (mils) er = Dielectric constant of the dielectric layer,Impedance Verification by TDR,Impedance Verification by TDR,Impedance Measured by HP 54754A,Flip-Chip Package,IBIS ModelI/O Buffer Information Spec

10、.,Simulation by 3com,Low Voltage CMOS,Un-terminated,Terminated,Low Voltage CMOS,Un-terminated,Terminated,Clock gen. Waveform,IDE Waveform,Crosstalk,When traces are close together, a change in current flow in one trace will cause current to flow in an adjacent trace Aggressor traces induce currents i

11、n adjacent victim traces Changes in current flow only occur during the aggressors rising and falling edges,Crosstalk,No Crosstalk,Impacts of Crosstalk,Crosstalk causes switching noise to appear on victim traces that would otherwise be quiet Crosstalk degrades the system noise budget when it occurs b

12、etween signals that are not part of the same signal group Since crosstalk only occurs when drivers are switching, the magnitude of crosstalk between bus bits is usually not important,Aggressor,Victim,Crosstalk-induced noise,Electrical Model for Crosstalk,Crosstalk - Impact on Bus Timing,Crosstalk be

13、tween adjacent bus bits affects edge speed (and therefore flight time) Denser routing makes better use of board space, but at the expense of larger variations in flight time Pre-layout crosstalk analysis helps the designer make the best tradeoff between routing density and signal integrity,Even Mode

14、,Reference,Odd Mode,D0 D1 D2,D0 D1 D2,D0 D1 D2,Example of Crosstalk,Risk in mass production,PCBs statistical quality Driving strength variation in chipset Passive components quality Temperature variation,Monte Carlo Analysis,A risk analysis instead of analytical method Used in complicate systems or too many parameters Suitable for mass production models,Example of Monte Carlo,Monte Carlo for Clock Signal,Conclusion,Impedance matching is important