第九章：0654.09c64x+SRIO.ppt

1、TMS320C64x+ Web Training09 SRIO,2009,Serial RapidIO,Peripheral: sRIO - Introduction,RapidIO? Packet switched point to point interconnect to connect processors, co-processors, memory and memory-mapped I/O, also board-to-board ”passing messages back and forth among the devices” Switch fabric connects

2、Non-proprietary protocol Objectives? Increased performance on our DSPs require increased peripheral bandwidth Robust communication with error detection features Scalability Non-software intensive Why serial? Pin count Longer distance Examples: backplane (board-to-board), multi-DSP architectures,sRIO

3、 Bus Comparison,sRIO - Overview,8,16 Parallel,Logical Specification,Transport Specification,Physical Specification,Globally Shared Memory,Message Passing,I/O System,Future Physical Specs,Congestion Control,Common Transport Spec,Inter-Operability Specification,1x/4x Serial,Layered approach allows sca

4、lability, re-usability and portability of software,3 Layered Architecture Physical defines electrical Characteristics, link flow control (CRC) Transport defines addressing scheme Logical defines packet format and operational protocol,Each layer Contains CAR/CSR Registers Accessible by host through M

5、aintenance operations,Rev 1.2 compliant 1.25, 2.5, or 3.125Gbps AC coupled interface (CML) 8b/10b Encoded Data Clock Recovery CRC Protection and HW error recovery Short Run and Long Run specifications,Future Logical Specs,sRIO - Packet Formats at Each Layer,Two Physical Layers 1X/4X Serial Interface

6、 Spec 8/16bit Parallel Bus Spec Common Transport 8 or 16 bit device IDs Destination routing not influenced by topology Logical Packet Types Scalable packets to 256 Byte payloads DMA protocol NWRITE, NWRITE_R, SWRITE, NREAD, ATOMIC Messaging protocol Maintenance operation,Physical layer,Transport lay

7、er,Logical layer,Type 6 - Streaming-Write Class,Type 11 Message Class,sRIO Supported Features,Read-modify-write, read, write, write w/response, streaming write, Messages, maintenance, Outgoing Atomic operations Support for 8b and 16b device ID Support of 34b in-coming addresses, 34, 50, and 66b outg

8、oing Support for data sizes: byte, half-word, word, double-word Direct IO transfers, data buffer FIFOs per priority DOORBELL interrupts Message passing transfers (Mailbox mapper) Data payloads upto 256B, single message upto 16 packets (4) 1X ports configurable to a 4X Serial RapidIO port Short Run (

9、low power) and Long Run (Backplane) Support for 1.25, 2.5, and 3.125Gbps rates (Non-concurrent) Error Management Extensions Congestion Control Extensions Xon/Xoff counters per deviceID,NOTE: Global Shared Memory specification (GSM) is NOT supported,sRIO Memory Management,RapidIO Peripheral can be Ex

10、ternally Mastered Allows data to be pushed into the device versus read in Two Logic protocols supported by RapidIO Direct I/O Logical Specification Target memory address is specified in the transferred packet Source device needs to know memory map of destination device Message Passing Logical Specif

11、ication Only device Ids and mailbox numbers are transferred in the packets, no memory addresses Destination Device is responsible for storing and managing memory space,sRIO Interrupt handling,Externally Mastered Peripheral No need to interrupt CPU to set up data transfer External device can push dat

12、a whenever Data transfers can span multiple packets Data handled by peripheral and stored in L2d Memory In-band Interrupt Notification After data is transferred and destination acknowledges source device, an interrupt can be specified Pre-defined write-able register or Doorbell Packet initiates CPU

13、interrupt Automatic Interrupt Generation for Message Passing Configurable rate,sRIO Error Management Extensions,Used to notify system software of faulty links. Defines counting and logging mechanism for transmission errors Allows programmable thresholds for system notification Defines protocol for e

14、xceeding thresholds and link recovery Defines new CSR bits and registers,sRIO Block Diagram,sRIO - Topologies,Dataflow (Push or pull) Memory Management Direct I/O Logical Specification Target memory address is specified Memory map knowledge required Message Passing Logical Specification Only mailbox

15、 numbers are specified Destination Device is responsible for storing and managing memory space,Interrupt Handling In-band Interrupt Notification (Doorbell) Automatic Interrupt Generation for Message Passing Configurable rate BIOS Support MSGQ (Message Queue) new module for local and remote message p

16、assing Transparent of the Transport,sRIO System architecture example,Ethernet ATM,Host Interface: Initialization Software download Configuration Signaling support Network mgmt,HostProcessor(RISC),Signaling Where the following are used to set the field #define RAPIDIOMQT_1X 0 #define RAPIDIOMQT_4X 1

17、RapidIO can be configured for different clock rates. Int portSpeed; Where the following are used to set the field #define RAPIDIOMQT_1_25GBPS 0 #define RAPIDIOMQT_2_5GBPS 1 #define RAPIDIOMQT_3_125GBPS 2 The parameters must match up from a system perspective since there is no auto-negotiation with R

18、apidIO. These fields are set in the first RapidIO MQTs open call.,sRIO Identification,Each core in the system must have a unique processor id. The ids are sequential and must start at zero. This is done to improve performance by allowing the fast indexing of routing tables. The processor Id is confi

19、gurable via BIOS configuration. Each RapidIO device in the system must have a unique Device Id. This can be an 8-bit or 16-bit. There are two fields in the RAPIDIOMQT_Params structure called Bool deviceId8Bit; / TRUE - 8 bit, FALSE - 16 bit Uint16 deviceId; All devices in the system must either be 8

20、-bit or 16-bit. RapidIO does not support a mixture. The RapidIO device id is set in the first RapidIO MQTs open call.,sRIO Multi-DSP environment,Here is an example configuration for three C6455 chips in a system.,C6455 Chip: Processor Id 0,Receiving on mailbox 0 and 1,No MQT,RapidIO MQT instanceDst Device Id = 0 x0211Tx MailBox = 0,RapidIO MQT instanceDst Device Id = 0 x0820Tx Mailbox = 0,MQT array,RapidIO MQT ISR,C6455 Chip: Processor Id 1,Receiving on mailbox 0 and 1,No MQT,RapidIO MQT instanceDst Device Id = 0 x0525Tx Mailbox = 0,RapidIO MQT ins