数字逻辑设计及应用教学课件：8-1 时序电路的设计实践xin

1、c h a p t e r 8Sequential Logic DesignPractices时序逻辑设计实践,数字逻辑设计及应用,Chapter 8,8.1 Sequential Circuit Documentation Standards(时序电路文档标准) 8.1.4 Timing Diagrams (定时图) and Specifications 8.2 Latches and Flip-Flops 8.2.1 SSI Latches and Flip-Flops(SSI型锁存器和触发器) applications： 8.2.2 Switch Debouncing开关消抖、 8.2.

2、4 Bus Holder Circuit总线保持 8.2.5 Multibit Registers and Latches多位寄存器和锁存器,Hold-time margin,Setup-time margin,8.2 Latches and Flip-Flops( 锁存器和触发器),SSI Latches and Flip-Flops,D Latches,Switch Debouncing (开关消抖),Push (开关闭合),Push (开关闭合),Ideal Case (理想情况),0,0,1,1,Push (开关闭合),0,0,1,1,Push (开关闭合),why this circ

3、uit should not be used with the high-speed CMOS devices? (为什么不应该同高速CMOS器件一起使用？),Bus Holder Circuit (总线保持电路),SDATA,4-bit Register(4位寄存器74x175),6位寄存器74x174,8-bit Register,74x374（三态输出）,74x377 （时钟使能）,74x374 （输出使能）,74x377（Clock Enable, 时钟使能）,二选一多路复用结构,register and latch 寄存器：edge trigger chracterastic 边沿触

4、发特性 锁存器：C有效期间输出跟随输入变化,8.4 Counters (计数器),Counter(计数器)(P710),The name counter is generally used for any clocked sequential circuit whose state diagram contains a single cycle, as in Figure 8-26. The modulus of a counter is the number of states in the cycle. A counter with m states is called a modulo-

5、m counter or, sometimes, a divide-by-m counter. A counter with a nonpower-of-2 modulus has extra states that are not used in normal operation.,计数器的分类 按时钟：同步、异步 按计数方式：加法、减法、可逆 按编码方式：二进制、十进制BCD码、循环码 计数器的功能 计数、分频、定时、产生脉冲序列、数字运算 本节内容 行波计数器、同步计数器 MSI型计数器及其应用 二进制计数器状态的译码,8.4.1 Ripple Counters,AN n-bit bin

6、ary counter can be constructed with just n flip-flops and no other components , for any value of n. 2bits binary counters normal binary counting sequence is 00-01-10-11-00,1,0,1,0,8.4.1 Ripple Counters,when a particular bit changes from 1 to 0, it generates a carry to the next most significant bit.

7、The counter is called a ripple counter because the carry information ripples from the less significant bits to the more significant bits, one bit at a time. 00-01-10-11-00,8.4.1 Ripple Counters（行波计数器）,use T flip-flop,考虑二进制计数顺序： 只有当第 i-1 位由10时， 第 i 位才翻转。,T flip-flop changes state (toggles) on every r

8、ising edge of its clock input.,Although a ripple counter requires fewer components than any other type of binary counter, it does so at a priceit is slower than any other type of binary counter. In the worst case, when the most significant bit must change, the output is not valid until time n tTQ af

9、ter the rising edge of CLK, where tTQ is the propagation delay from input to output of a T flip-flop.,Ripple Counters,速度慢，,最坏情况，第n位要经过 ntTQ 的延迟时间, 异步时序,8.4.2 Synchronous Counters(同步计数器),A synchronous counter connects all of its flip-flop clock inputs to the same common CLK signal, so that all of the

10、 flip-flop outputs change at the same time, after only tTQ ns of delay.,synchronous counter同步二进制加法计数器,在多位二进制数的末位加 1， 仅当第 i 位以下的各位都为 1 时， 第 i 位的状态才会改变。 最低位的状态每次加1都要改变。,利用有使能端的 T 触发器实现：,Q* = ENQ + ENQ = EN Q,通过EN端进行控制， 需要翻转时，使 EN = 1 ENi = Qi-1 Qi-2 Q1 Q0,EN0 = ?,1,synchronous counter,如何加入使能端？,synchro

11、nous counter with enable input 有使能端的同步计数器,同步二进制加法计数器,对于D触发器：Q* = D,Di = (Qi-1 Q1 Q0) Q,= EN Q,考虑 T 触发器：Q* = EN Q,利用 D 触发器实现：,D0 = 1 Q = Q,8.4.3 MSI counters and applicationsMSI型计数器及应用-同步4位二进制计数器74x163,8.4.3 MSI Counters and Applications4位二进制计数器74x163,74x161异步清零,Q0,Q1,Q2,Q3,D0,D1,D2,D3,LD_L,CLR_L,QA,

12、Synchronous clear and load functions 同步清零和预置数功能,0,1,0,0,0,0,0,LD_L,CLR_L,QA,0,0,1,0,A,0,A,1,1,X,Synchronous clear and load functions 同步清零和预置数功能,LD_L,CLR_L,QA,Enables and ripple carry out (RCO) signals 使能信号 与进位信号,1,0,0,1,0,QAN,QAN,1,ENP.ENT=1,QAN,LD_L,CLR_L,QB,1,0,0,1,0,1,QA,QBN,Enables and ripple carry out (RCO) signals 使能信号 与进位信号,Connections for the 74X163 to operate in a free-runni