电脑维修资料：820E主板电路图.pdfVIP

5-23-2000_9:181 revision 0.5 fcpga 2 rimm ich2 reference schematics drawn by: last revised:sheet: folsom, california 95630 1900 prairie city road 87654321 a b c d 12345678 d c b a pcg platform design rev: 0.5 project: of 40 title: intel(r) 820e chipset 2 dimm fcpga reference board r pcg aecamino2 note that these schematics are preliminary and are subject to change. intel(r) 820e chipset these schematics are provided “as is” with no warranties whatsoever, including any warranty of merchantability, fitness for any particular purpose, or any warranty otherwise arising out of proposal, specification or samples. information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intels terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the intel 82820e chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. intel may make changes to specifications and product descriptions at any time, without notice. copyright intel corporation 2000. *third-party brands and names are the property of their respective owners. titlepage cover sheet1 block diagram2 processor connector3, 4 clock synthesizer5 mch6, 7 ich28, 9 fwh10 rimm sockets11 super i/o12 audio13,14 lan15,16,17,18, lan19,20,21,22 system23 agp connector24 pci connectors25,26 ide connectors27 usb connectors28 parallel port29 serial ports30 keyboard/mouse/floppy ports31 game port32 vrm33 voltage regulators34, 35 pow er connector36 agtl termination37 pci/agp pullups/pulldow ns38 rambus decoupling39 decoupling40, 41 revision history42 25-23-2000_9:18 block diagram drawn by: last revised:sheet: folsom, california 95630 1900 prairie city road 87654321 a b c d 12345678 d c b a pcg platform design rev: 0.5 project: of 40 title: intel(r) 820e chipset 2 dimm fcpga reference board r pcg aecamino2 lpc bus ctrl addraddr ctrl data agp bus pci conn 3 pci conn 1 pci conn 2 pci conn 4 pci addr/data pci cntrl ac97 link block diagram clockvrm agp mch usb ide primary ide secondary usb port 1 usb port 2 ac97 audio modem sio parallelgame connfloppykeyboard mouse serial 1 serial 2 fwh device table processor rambus ich2 ultradma/100 data vterm rimm 0 rimm 1 drcg 82562eh/et cnr lan referencedevicegatessheet designatortypeusednumber u1lm488014 u2ad188113 u374lvc08aa, b36 u4, u6gd7523230 u88256217 u1082820 (mch)6, 7 u11ck1335 u12drcg5 u1382820 (ich)8, 9 u1474lvc07aa, b, c, d, e 7, 23, 34, 35 u1574lvc14aa, b, c, d, e36 u16fwh10 u17lpc47b27x12 u1874ls132b, c34, 36 u1974lvc07aa, c, d23, 27 u2074lvc06aa, b, c36 u2174hc0315 u2582562em18 u26ffb390423 u27h1138_argonite20 u28a03449-00119 3-20-2000_10:153 processor connector vid0 vid1 vid2 vid3 33 vid3:0 0.1uf c80 jp16 1 2 3 rs#0 rs#1 rs#2 6 rs#2:0 hreq#0 hreq#1 hreq#2 hreq#3 hreq#4 6 hreq#4:0 ha#3 ha#4 ha#5 ha#6 ha#7 ha#8 ha#9 ha#10 ha#11 ha#12 ha#13 ha#14 ha#15 ha#16 ha#17 ha#18 ha#19 ha#20 ha#21 ha#22 ha#23 ha#24 ha#25 ha#26 ha#27 ha#28 ha#29 ha#30 ha#31 6,37 ha#31:3 hd#63 hd#62 hd#61 hd#60 hd#59 hd#58 hd#57 hd#56 hd#55 hd#54 hd#53 hd#52 hd#51 hd#50 hd#49 hd#48 hd#47 hd#46 hd#45 hd#44 hd#43 hd#42 hd#41 hd#40 hd#39 hd#38 hd#37 hd#36 hd#35 hd#34 hd#33 hd#32 hd#31 hd#30 hd#29 hd#28 hd#27 hd#26 hd#25 hd#24 hd#23 hd#22 hd#21 hd#20 hd#19 hd#18 hd#17 hd#16 hd#15 hd#14 hd#13 hd#12 hd#11 hd#10 hd#9 hd#8 hd#7 hd#6 hd#5 hd#4 hd#3 hd#2 hd#1 hd#0 6,37 hd#63:0 skt1 aj37 al37 am36 al35 ak28 ah22 ah26 aa33 aa35 an21 e23 s33 s37 u35 u37 al17 al19 ah18 ah16 ak18 p6 s1 j1 f16 e25 a27 a25 t6 c17 c23 a19 c27 c19 c21 a23 d16 a13 c25 s3 c13 a17 a15 a21 c11 a11 a7 d12 d14 c15 u1 d10 d8 a9 c9 b2 c7 c1 f6 c5 j3 m6 a3 a5 f12 e1 e3 k6 g3 f8 g1 l3 n1 h6 p4 r4 h4 u3 n3 l1 q1 m4 q3 t4 w1 al9 ah10 al15 an9 ah8 ah12 af4 w3 ac1 x6 ad4 aa3 ak8 z4 ak6 aa1 y3 af6 ab4 ab6 ae3 aj1 ac3 ag3 z6 ae1 an7 al5 ak14 al7 an5 ak10 ah6 a29 e29 c29 e31 a31 a33 c31 c33 vcc12 vtt1_5 drawn by: last revised:sheet: folsom, california 95630 1900 prairie city road 87654321 a b c d 12345678 d c b a pcg platform design rev: 0.5 project: of 40 title: intel(r) 820e chipset 2 dimm fcpga reference board r pcg aecamino2 vccvid;b26,c3,ak2,af2,ab2,t2,p2,k2,f4,e5,am4,ae5,aa5,w5,s5,n5,j5,f2,d6,b6 vccvid;am8,aj9,e9,b10,am12,aj13,e13,b14,am16,aj5,aj17,e17,b18,am20,aj21,d20,f22 vccvid;am24,aj25,d24,f26,am28,aj29,d28,ak34,f30,b30,am32,ah32,z32,v32,r32 vccvid;m32,h32,af34,ab34,x34,t34,p34,k34,f34,b34,ah36,b22,v36,r36,h36,d36,d32 vccvid;ad32,ah24,f14,k32,aa37,y35 vtt1_5;ah20,ak16,al21,an11,an15,g35,al13 gnd;am34,ah2,ad2,z2,v2,m2,d18,h2,d2,al3,ak4,ag5,ac5,y5,u5,q5,l5,g5,d4,b4 gnd;am6,aj7,e7,b8,am10,aj11,e11,b12,am14,aj15,e15,b16,am18,aj19,e19,f20,b20 gnd;am22,aj23,d22,f24,b24,am26,aj27,d26,f28,b28,am30,d30,af32,ab32,x32,t32 gnd;p32,f32,b32,ah34,ad34,z34,v34,r34,m34,h34,d34,ak36,af36,x36,t36,p36,k36 part 1 370-pin socket dep0# dep1# dep2# dep3# dep4# dep5# dep6# dep7# ha#10 ha#11 ha#12 ha#13 ha#14 ha#15 ha#16 ha#17 ha#18 ha#19 ha#20 ha#21 ha#22 ha#23 ha#24 ha#25 ha#26 ha#27 ha#28 ha#29 ha#3 ha#30 ha#31 ha#32 ha#33 ha#34 ha#35 ha#4 ha#5 ha#6 ha#7 ha#8 ha#9 hd#0 hd#1 hd#10 hd#11 hd#12 hd#13 hd#14 hd#15 hd#16 hd#17 hd#18 hd#19 hd#2 hd#20 hd#21 hd#22 hd#23 hd#24 hd#25 hd#26 hd#27 hd#28 hd#29 hd#3 hd#30 hd#31 hd#32 hd#33 hd#34 hd#35 hd#36 hd#37 hd#38 hd#39 hd#4 hd#40 hd#41 hd#42 hd#43 hd#44 hd#45 hd#46 hd#47 hd#48 hd#49 hd#5 hd#50 hd#51 hd#52 hd#53 hd#54 hd#55 hd#56 hd#57 hd#58 hd#59 hd#6 hd#60 hd#61 hd#62 hd#63 hd#7 hd#8 hd#9 req#0 req#1 req#2 req#3 req#4 resvtt0 resvtt1 resvtt2 resvtt3 resvtt4 resvtt5 resvtt6 resvtt7 rs#0 rs#1 rs#2 vid0 vid1 vid2 vid3 gnd;f36,a37,ac33,y37 fan header 3-20-2000_10:15 processor connector 4 0.1uf c433 0.1uf c432 0.1uf c434 0.1uf c435 0.1uf c431 tdo r511 22 c428 10pf r514 1k r515 47 r516 150 4.7uf c436 2 1 0.1uf c429 c437 20% 33uf 21 4.7uh l26 47 r517 r520 680 tdi r122 r121 j28 3029 2827 2625 2423 2221 2019 1817 1615 1413 1211 109 87 65 4 21 3 tck tms cpurst#_r itp_pon dbrst#_r itprdy#_r itpreq# 75-1% r131 150-1% r130 4,6 gtlref adm1021 u9 2 3 6 9 10 11 12 13 14 15 16 5 4 1 7 8 330 r529 150 r535 330 r530 1k r523 1k r524 4,6,8,37cpurst# 36 dbreset#240 r513 4 tck_r0k r512 4 tms_r 4 tms_r trst# 4 tck_r itprdy# 9 thrm# 8,38 apicd0 8,38 apicd1 5 apicclk_cpu 5 cpuhclk 8,36 pwrgood 4,6,8,37 cpurst# 4,6 gtlref 6,37 bnr# 6,37 bpri# 6,37 htrdy# 6,37 defer# 6,37 hlock# 6,37 drdy# 6,37 hitm# 6,37 hit# 6,37 dbsy# 6,37 hads# 38 flush# 8,9,33,36 vrm_pwrgd 5,7 sel133/100# 38 br0# 8 a20m# 8 stpclk# 8 cpuslp# 8 lint0 8 lint1 8,10 hinit# 8,38 ferr# 8 ignne# 38 slewctrl 38 rttctrl 36 vcoredet# 5 itpclk r518 240 thermdp_r thermdn_rthermdn thermdp 4 thermdn 4 thermdp 9,11,15,38 smbclk_core 9,11,15,38 smbdata_core 1% 182 r519 r521 110 1% 1 r544 86 r522 330 r547 100pf c475 8 smi# 56 r545 33 r546 skt1 an3 ak32 al33 n33 e35 c35 e37 g33 a35 j37 an33 an37 an35 ab36 ak22 ak12 ad6 v6 r6 k4 f18 e33 e21 z36 ad36 an25 al31 al29 ah28 ag35 aj35 ah30 e27 s35 q33 n37 n35 l33 g37 r2 y1 w35 f10 am2 ak30 q37 q35 ac37 an23 al1 aj3 x2 x4 ah4 ak26 u33 w33 l35 j35 j33 ak20 l37 m36 ag33 ag37 ae35 al23 al25 ae37 ac35 ag1 an27 an19 al27 c37 y33 aj31 aj33 an29 an17 ah14 b36 v4 w37 an13 al11 ak24 an31 ae33 vtt1_5 vcc3_3 vcmos1_5 vtt1_5 vtt1_5 vtt1_5 vtt1_5 + drawn by: last revised:sheet: folsom, california 95630 1900 prairie city road 87654321 a b c d 12345678 d c b a pcg platform design rev: 0.5 project: of 40 title: intel(r) 820e chipset 2 dimm fcpga reference board r pcg aecamino2 + vtt1_5 0k 0k vtt1_5 gnd8 gnd7 nc1 dxn nc5 nc16 stby# smbclk nc13 smbdata alert# add0 nc9 add1 dxp vcc2 vcc3_3sby_mth vtt1_5 vcmos1_5 vccvid part 2 370-pin socket a20m# ads# aerr# ap0# ap1# bclk berr# binit# bnr# bpri# bsel0# bsel1# clkref cpupres# dbsy# defer# drdy# edgctrl ferr# flush# hit# hitm# ierr# ignne# init# lint0/intr lint1/nmi lock# picclk picd0 picd1 pll1 pll2 pwrgood reset# reset2# resvd21 resvd22 resvd23 rp# rsp# rsrvd10 rsrvd11 rsrvd12 rsrvd13 rsrvd15 rsrvd16 rsrvd17 rsrvd18 rsrvd19 rsrvd20 rsrvd7 rsrvd8 rsrvd9 rttcntr slewcntr slp# smi# stpclk# thermtrip# thrmdn thrmdp trdy# v1_5 v2_5 vcoredet vref0 vref1 vref2 vref3 vref4 vref5 vref6 vref7 v_cmos tdi tdo trst# preq# prdy# bp2# bp3# bpm0# bpm1# rsrvd6 tck tms resvd24 br0# itp test port option place 4-0.1uf within 500 mils of the processor input pinsplace c431 near vcmos pin 3-20-2000_14:02 clock synthesizer 5 jp20 10k r230 c364 82pf 4,7 sel133/100# 4pf c363 ck133_xin sio_14mhz_r ihc_14mhz_r ihc_48mhz_r test_clk66_r ich_clk66_r mch_clk66_r sio_pclk7_r fwhpclk_r pclk5_r pclk4_r pclk3_r pclk2_r pclk1_r ichpclk_r itpclk_r ck133_xout vcc_3_3_ck133_fb pcistop# cpustop# ck133_pwrdwn# spread# sel0 vcc2_5_ck133_fb apicclk_r picclk_r 33 r211 pclk5 10k r206 10k r203 jp15 7 hclkout 7 rclkout 25 pclk1 cpuhclk 4 mchclk 6 14.318mhz y3 21 22 r188 33 r165 33 r169 33 r186 33 r191 33 r183 26 pclk3 26 pclk4 10 fwhpclk 9 ich_14mhz r147 22 12 sio_pclk7 agpclk_conn 24 r195 33 7 mch_clk66 22 r221 r200 51-1%51-1% r185 9 ich_48mhz 33 r194 10k r202 8 mult0_gpio jp17 r196 10k r192 10k 33 r201 33 r187 fbhs01l l20 21 l21 fbhs01l 12 22 r155 r170 30 9 ich_clk66 r150 22 8 ichpclk 25 pclk2 drcg_clk drcg_clkb# r205 39-1% r182 39-1% clktm_rd 0.1uf c207 0.1uf c215 c223 0.1uf 0.1uf c186 0.1uf c198 0.1uf c206 0.1uf c214 10pf c185 10pf c189 0.1uf c199 0.1uf c192 0.1uf c190 0.1uf c180 c204 0.1uf 0.1uf c220 10uf c209 0.1uf c196 10uf c171 10uf c170 33 r210 12 sio_14mhz r199 10k r224 220 r197 10k stopb# 10k r219 10k r204 mult0 drcg_pwrdwn# r156 22 cpu_div2_1_r r148 22 4 itpclk 33 r164 cpu_div2 jp14 sel1 vcc3_3_drcg_fb fbhs01l l22 12 11 clktm# 11 clktm c208 0.1uf u11 5 55 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 4 3 2 1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 56 drcg+ u12 21 17 2 12 11 24 23 22 20 18 16 15 14 10 7 6 9 8 5 4 3 1 13 0.1uf c205 4 apicclk_cpu 8 apicclk_ich 33 r220 cpuclk3_r cpuhclk_r r151 30 cpu_div2_2_r 30 r166 apic2_r 33 r189 10pf c476 10pf c477 33 r184 jp13 3 2 1 jp19 jp26 1 2 3 8 drcg_ctrl 9 mult1_gpio r217 10k mult1 test_clk66 vcc3_3 drawn by: last revised:sheet: folsom, california 95630 1900 prairie city road 87654321 a b c d 12345678 d c b a pcg platform design rev: 0.5 project: of 40 title: intel(r) 820e chipset 2 dimm fcpga reference board r pcg aecamino2 vcc3_3 vcc3_3 xtal vcc3_3 vcc2_5 vcc2_5 vcc3_3 vcc1_8 vcc1_8 2_5v ck133 vdd25v_1 apic1 apic0 vss7 vdd25v_2 cpu_div2_1 cpu_div2_2 vss8 vdd25v_3 cpuclk3 cpuclk2 vss9 vdd25v_4 cpuclk1 cpuclk0 vss10 vdd3v_6 vss11 cpustop# pwrdwn# spread# sel1 sel0 vdd3v_7 vss1 ref0 ref1 vdd3v_1 xtal_out vss2 pciclk_f pciclk1 vdd3v_2 pciclk2 pciclk3 vss3 pciclk4 pciclk5 vdd3v_3 pciclk6 pciclk7 vss4 vss5 3v66_0 3v66_1 vdd3v_4 vss6 3v66_2 3v66_3 vdd3v_5 vss12 48mhz apic2 xtal_in sel133/100# pcistop# gnd vddir vddp gndp gndi gndc vddc pclkm vddipd mult1 mult0 vddo1 clkb# clk vddo2 s1 s0 stopb# pwrdn# refclk gndo1 gndo2 synclkn 19 nc vcc3_3 place c364 next to vddp jp19 is for debug only.clktm and clktm# rc network must use 5% or better tolerance components. all jumpers may not be required, but are included for test purposes. for debug. provide at least one 0.1uf decoupling cap per power pin. vddir pin on drcg should be decoupled at the component with a 0.1uf cap. keep stubs on unused outputs as short as possible. tie cpuclk and mchclk outputs together. clock synthesizer no stuff c363 no stuff r220 jp13 is for debug only. s el133/100# jp 15jp 17function 0inina ll outputs tri-s tate 0ino utres erved 0o utina ctive 100m hz , 48m hz p ll inac tive 0o uto uta ctive 100m hz , 48m hz p ll active 1inintest m ode 1ino utres erved 1o utina ctive 133m hz ,48m hz p ll inactive 1o uto uta ctive 133m hz ,48m hz p ll ac tive* s p rd s p e c tj p 1 4 e n a b le d *in d is a b le do u t h o s t b u s /r a m b u sj p 1 3 1 0 0 /4 0 0o u t 1 3 3 /4 0 02 -3 3-20-2000_14:02 mch 6 ramref 6,11 ramref_r 0.1uf c183 0.1uf c158 hd#63:0 3,37 hd#0 hd#1 hd#2 hd#3 hd#4 hd#5 hd#6 hd#7 hd#8 hd#9 hd#10 hd#11 hd#12 hd#13 hd#14 hd#15 hd#16 hd#17 hd#18 hd#19 hd#20 hd#21 hd#22 hd#23 hd#24 hd#25 hd#26 hd#27 hd#28 hd#29 hd#30 hd#31 hd#32 hd#33 hd#34 hd#35 hd#36 hd#37 hd#38 hd#39 hd#40 hd#41 hd#42 hd#43 hd#44 hd#45 hd#46 hd#47 hd#48 hd#49 hd#50 hd#51 hd#52 hd#53 hd#54 hd#55 hd#56 hd#57 hd#58 hd#59 hd#60 hd#61 hd#63 hd#62 grcomp mch_hlcomp pcirst# 8,10,11,12,24,25,26,27 mchclk 5 3 hreq#4:0 hreq#4 hreq#3 hreq#2 hreq#1 hreq#0 rs#2:0 3 rs#2 rs#1 rs#0 htrdy# 4,37 hlock# 4,37 hitm# 4,37 hit# 4,37 drdy# 4,37 defer# 4,37 dbsy# 4,37 bpri# 4,37 bnr# 4,37 hads# 4,37 cpurst# 4,8,37 8 hubref 24 conn_agpref 24 mch_agpref r190 162-1% ramref 6,11 100-1% r168 40.2-1% r180 40.2-1% r129 0.1uf c155 0.1uf c191 0.1uf c203 c182 470pf 562-1% r181 0.01uf c194 c187 470pf u10 v2 y1 w2 c3 v12 e11 e10 u14 e20 t15 a18 f20 g2 e3 e4 g4 h1 e2 c1 e5 f4 f3 e1 d3 f1 f2 d1 g1 f5 d2 p4 m5 n4 p3 p2 n1 p1 m4 n5 m1 m2 m3 n2 l2 k4 l4 k3 k5 j2 k1 j5 l1 j4 h2 h5 k2 g5 h4 h3 j1 w13 v14 y14 u12 u11 w14 y12 y13 u13 t11 w12 v10 u10 t12 t10 y11 t9 w11 y9 u9 v8 y10 w10 u8 w9 t7 w8 t8 y7 y8 u7 w7 t6 w6 v6 u6 w5 y6 t5 v5 t4 y5 y4 t3 u4 v4 w3 w4 u2 u3 y3 t2 u1 w1 y2 v1 r5 t1 p5 r4 r1 r2 1k-1% r154 1k-1% r159 mch_agpref_cg mch_agpref_cv 4 gtlref ha#3 ha#4 ha#5 ha#6 ha#7 ha#30 ha#31 ha#29 ha#28 ha#27 ha#26 ha#25 ha#24 ha#23 ha#22 ha#21 ha#20 ha#19 ha#18 ha#17 ha#16 ha#15 ha#14 ha#13 ha#12 ha#11 ha#10 ha#9 ha#8 3,37 ha#31:3 r160 80.6-1% r153 80.6-1% drawn by: last revised:sheet: folsom, california 95630 1900 prairie city road 87654321 a b c d 12345678 d c b a pcg platform design rev: 0.5 project: of 40 title: intel(r) 820e chipset 2 dimm fcpga reference board r pcg aecamino2 vddq vcc1_8 vcc1_8 vddq;f15,r15,j17,l17,n17,t17 mch_096 gnd;d9,j9,k9,l9,m9,v9,b10,j10,k10,l10,m10,c11,j11,k11,l11 gnd;p19,t19,d20 gnd;b15,d15,b16,d16,e16,f16,a17,e18,v18,a19,h19,k19,m19 hd#0 hd#1 hd#2 hd#3 hd#4 hd#5 hd#6 hd#7 hd#8 hd#9 hd#10 hd#11 hd#13 hd#15 hd#16 hd#17 hd#18 hd#19 hd#20 hd#21 hd#22 hd#23 hd#24 hd#25 hd#26 hd#27 hd#28 hd#29 hd#30 hd#31 hd#32 hd#33 hd#34 hd#35 hd#36 hd#37 hd#38 hd#39 hd#40 hd#41 hd#42 hd#43 hd#44 hd#45 hd#46 hd#47 hd#48 hd#49 hd#50 hd#51 hd#52 hd#53 hd#54 hd#55 hd#56 hd#57 hd#58 hd#59 hd#60 hd#61 hd#62 hd#63 ha#3 ha#4 ha#5 ha#6 ha#7 ha#8 ha#9 ha#10 ha#11 ha#12 ha#13 ha#14 ha#15 ha#16 ha#17 ha#18 ha#19 ha#20 ha#21 ha#22 ha#23 ha#24 ha#25 ha#26 ha#27 ha#28 ha#29 ha#30 ha#31 cpurst# ads# bnr# bpri# dbsy# defer# drdy# hit# hitm# hlock# htrdy# rs#0 rs#1 rs#2 hreq#0 hreq#1 hreq#2 hreq#3 hreq#4 rstin# hubref agpref ramrefb ramrefa gtlrefb gtlrefa hd#12 hd#14 hclkin test/grcomp hlcomp vcc1_8;d4,e6,f6,g6,e7,r6,r7,e8,e9,d10,d11,e12 vcc1_8;e13,e14,f14,t14,e15,p15,b17,c17,c19 gnd;a1,a3,g3,j3,l3,n3,r3,v3,b4,d5,l5,u5,b6,d6,d7,v7,b8,d8 gnd;m11,v11,c12,d12,j12,k12,l12,m12,b13,d13,v13,t13,d14 hosthost place r129 and r180 less than 0.5“ from mch using 10 mil trace. mch place mch_agpref circuit near the mch. 3-20-2000_14:02 mch 7 4.7k r248 pwrok 8,9,34,36 u14 14 7 1312 hl10 7,8 gad1 gad2 gad3 gad4 gad5 gad6 gad7 gad8 gad9 gad10 gad11 gad12 gad13 gad14 gad15 gad16 gad17 gad18 gad19 gad20 gad21 gad22 gad23 gad24 gad25 gad26 gad27 gad28 gad29 gad30 gad31 24 gad31:0 gad0 hl2 hl1 8 hl10:0 hl0 hl10 hl9 hl8 hl7 hl6 hl5 hl4 hl3 hl_stb 8 hl_stb# 8 gc/be#2 gc/be#1 gc/be#0 gc/be#3:0 24 gc/be#3 24,38 gtrdy# 24,38 girdy# 24,38 gdevsel# 24,38 gframe# gpar 24,38 24,38 gstop# sbstb# 24,38 adstb1 24,38 adstb0 24,38 wbf# 24,38 24,38 pipe# 24,38 greq# 24,38 ggnt# st2 st0 st1 st2:0 24 5 mch_clk66 24,38 rbf# adstb#0 24,38 adstb#1 24,38 sbstb 24,38 hclkout 5 rclkout 5 24 sba7:0 sba1 sba3 sba4 sba5 sba6 sba7 sba2 sba0 4,5 sel133/100# r209 8.2k 8.2k r227 7 pwrok_ctrl 11 ldqa8:0 ldqa1 ldqa0 ldqa2 ldqa3 ldqa4 ldqa5 ldqa6 ldqa7 ldqa8 11 ldqb8:0 ldqb0 ldqb1 ldqb2 ldqb3 ldqb4 ldqb5 ldqb6 ldqb7 ldqb8 11 lrow2:0 lrow0 lrow1 lrow2 11 lclktm# 11 lclkfm 11 lclkfm# 11 lsio 11 lcol4:0 lcol1 lcol2 lcol3 lcol4 lcol0 11 lclktm u10 y19 y20 w17 y18 w18 a16 a9 b9 c9 f19 c4 a4 b5 a5 c5 a6 c6 b7 c7 c16 a15 c15 b14 c14 a14 c13 a13 a2 b1 c20 d19 d18 c18 d17 a20 b18 b19 b20 e19 e17 f18 a7 c8 a8 a10 c10 b11 a11 a12 b12 b3 b2 c2 w20 v17 v20 w19 v19 u16 r19 r18 h20 j19 y17 y15 w15 v15 v16 w16 y16 u15 k16 m18 m20 n20 n19 l16 r16 n18 l20 h16 u19 u20 t18 u18 t16 u17 r17 t20 r20 p16 p20 n16 p17 m16 p18 m17 l18 k20 l19 j18 k18 k17 j16 j20 h18 h17 g20 g16 g19 g17 g18 f17 q10 mmbt3904lt1 b c e 11 lcmd lcmd mmbt3904lt1 q9 e c b 4.7k r229 q14 mmbt3904lt1 b c e 11 lsck 7 pwrok_ctrl drawn by: last revised:sheet: folsom, california 95630 1900 prairie city road 87654321 a b c d 12345678 d c b a pcg platform design rev: 0.5 project: of 40 title: intel(r) 820e chipset 2 dimm fcpga reference board r pcg aecamino2 vcc3_3sby sn74lvc07a gnd vcc vcc3_3sby mch_096 hub agp memory agp g_ad0 g_ad1 g_ad2 g_ad3 g_ad4 g_ad5 g_ad6 g_ad7 g_ad8 g_ad9 g_ad10 g_ad11 g_ad12 g_ad13 g_ad14 g_ad15 g_ad16 g_ad17 g_ad18 g_ad19 g_ad20 g_ad21 g_ad22 g_ad23 g_ad24 g_ad25 g_ad26 g_ad27 g_ad28 g_ad29 g_ad30 g_ad31 g_c/be#0 g_c/be#1 g_c/be#2 g_c/be#3 g_frame# g_devsel# g_irdy# g_trdy# g_stop# g_par g_req# g_gnt# pipe# rbf# wbf# st0 st1 st2 ad_stb0 ad_stb#0 ad_stb1 ad_stb#1 sba7 sba6 sba5 sba4 sba1 sba0 sio sck cmd cfm# cfm ctm# ctm rq7 rq6 rq2 rq1 rq0 hl1 hl2 hl3 hl4 hl5 hl6 hl7 hl8 hl9 hl10 hl_stb hl_stb# rclkout hclkout dqa0 dqa1 dqa2 dqa3 dqa4 dqa5 dqa6 dqa7 dqb0 dqb1 dqb2 dqb3 dqb4 dqb5 dqb6 dqb7 dqb8 hl0 rq3 rq4 rq5 dqa8 clk66 sba2 sba3 sb_stb sb_stb# 1 3 2 1 3 2 v