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资料1：8位D/A转换器DAC08321. 引脚及其功能DAC0832是双列直插式8位D/A转换器。能完成数字量输入到模拟量(电流)输出的转换。图1-1和图1-2分别为DAC0832的引脚图和内部结构图。其主要参数如下：分辨率为8位，转换时间为1s，满量程误差为1LSB，参考电压为(+10-10)V，供电电源为(+5+15)V，逻辑电平输入与TTL兼容。从图1-1中可见，在DAC0832中有两级锁存器，第一级锁存器称为输入寄存器，它的允许锁存信号为ILE，第二级锁存器称为DAC寄存器，它的锁存信号也称为通道控制信号 /XFER。图1-1、DAC0832引脚图图1-1中，当ILE为高电平，片选信号 /CS 和写信号 /WR1为低电平时，输入寄存器控制信号为1，这种情况下，输入寄存器的输出随输入而变化。此后，当 /WR1由低电平变高时，控制信号成为低电平，此时，数据被锁存到输入寄存器中，这样输入寄存器的输出端不再随外部数据DB的变化而变化。对第二级锁存来说，传送控制信号 /XFER 和写信号 /WR2同时为低电平时，二级锁存控制信号为高电平，8位的DAC寄存器的输出随输入而变化，此后，当 /WR2由低电平变高时，控制信号变为低电平，于是将输入寄存器的信息锁存到DAC寄存器中。图1-1中其余各引脚的功能定义如下：(1)、DI7DI0 ：8位的数据输入端，DI7为最高位。(2)、IOUT1 ：模拟电流输出端1，当DAC寄存器中数据全为1时，输出电流最大，当 DAC寄存器中数据全为0时，输出电流为0。(3)、IOUT2 ：模拟电流输出端2， IOUT2与IOUT1的和为一个常数，即IOUT1IOUT2常数。(4)、RFB ：反馈电阻引出端，DAC0832内部已经有反馈电阻，所以 RFB端可以直接接到外部运算放大器的输出端，这样相当于将一个反馈电阻接在运算放大器的输出端和输入端之间。(5)、VREF ：参考电压输入端，此端可接一个正电压，也可接一个负电压，它决定0至255的数字量转化出来的模拟量电压值的幅度，VREF范围为(+10-10)V。VREF端与D/A内部T形电阻网络相连。(6)、Vcc ：芯片供电电压，范围为(+5 15)V。(7)、AGND ：模拟量地，即模拟电路接地端。(8)、DGND ：数字量地。图1-2、DAC0832内部结构图2、 DAC0832的工作方式DAC0832可处于三种不同的工作方式：1、 直通方式 ：当ILE接高电平，、和都接数字地时，DAC处于直通方式，8位数字量一旦到达DI7DI0输入端，就立即加到8位D/A转换器，被转换成模拟量。例如在构成波形发生器的场合，就要用到这种方式，即把要产生基本波形的数据存在ROM中，连续取出送到DAC去转换成电压信号。2、 单缓冲方式 ：只要把两个寄存器中的任何一个接成直通方式，而用另一个锁存器数据，DAC就可处于单缓冲工作方式。一般的做法是将和都接地，使DAC寄存器处于直通方式，另外把ILE接高电平，接端口地址译码信号，接CPU的信号，这样就可以通过一条MOVX指令，选中该端口，使和有效，启动D/A转换。3、 双缓冲方式 ：主要在以下两种情况下需要用双缓冲方式的D/A转换。l 需在程序的控制下，先把转换的数据输入输入缓存器，然后在某个时刻再启动D/A转换。这样，可先选中端口，把数据写入输入寄存器；再选中端口，把输入寄存器内容写入DAC寄存器，实现D/A转换。l 在需要同步进行D/A转换的多路DAC系统中，采用双缓冲方式，可以在不同的时刻把要转换的数据打入各DAC的输入寄存器，然后由一个转换命令同时启动多个DAC转换。先用3条输出指令选择3个端口，分别将数据写入各DAC的输入寄存器，当数据准备就绪后，再执行一次写操作，使变低同时选通3个D/A的DAC寄存器，实现同步转换。3、DAC0832的应用图1-3为单片机和DAC0832直通方式输出连接图，运放输出电路输出电压为 UOUT(D/256)*VREF, 例如上图中向DAC0832传送的8位数据量40H(01000000B), 则输出电压UOUT=(64/256)*5V=1.25V，其输出过程可用MOV P1 , #40H一条指令完成。 图1-3、单片机和DAC0832直通方式输出连接图资料2：ADC804的性能特点ADC804型8位全MOS 转换器。它是中速廉价型产品之一。片内有三态数据输出锁存器，与微处理器兼容，输入方式为单通道，转换时间约为100s。它的非线形误差为1LSB。电源电压为单一+5V。1、ADC0804的引脚及其功能ADC0804的典型外部接线图如图2-1所示。被转换的电压信号从和输入，允许此信号是差动的或不共地的电压信号,模拟地和数字地分别设置引入端,使数字电路的地电流不影响模拟信号回路，以防止寄生耦合造成的干扰。参考电压可以由外部电路供给，从“”端直接送入。当电源准确、稳定时，也可作参考基准。此时，由ADC0804片内部设置的分压电路可自行提供参考电压(2.5V)，“”端不必外接电源，浮空即可。 ADC0804片内有时钟电路，只要在外部“CLKR”和“CLK”两端外接一对电阻电容即可产生转换所需要的时钟，其振荡频率为RC。其典型应用参数为：R=10k，C=150pF，640kHz，每秒钟可转换1万次。若采用外部时钟，则外部可从CLK端送入，此时不接R、C。 是片选端，是控制芯片启动的输入端；是转换结束信号输出端，输出电平高跳到低表示本次转换已经完成，可作为中断或查询信号。如果和端与端相连，则ADC0804就处于自动循环转换状态。为转换结果读出控制端，当它与同时为低电平时，输出数据锁存器DB0DB7各端上出现8位并行二进制数码，以表示结果。图2-1、ADC0804引脚图2、ADC0804转换器的时序及接口电路ADC0804转换器的时序如下。=0时，允许进行转换。由低跳高时转换开始，8位逐次比较需用88=64个时钟周期，再加上控制逻辑操作，一次转换需要6673个时钟周期。ADC0804与AT89C51单片机的接口电路见图2-2：图2-2、单片机和0804接口电路0804由于具有三态输出锁存器，可直接驱动数据总线，故与AT89C51接口电路十分简单，直接连接成上图即可。当与同时有效时便启动转换，转换结束时产生信号，可供输出查询或中断信号。在和共同控制下可以读取转换结果数据。在转换过程中，如果再次启动转换器，则终止正在进行的转换，进入新的转换，在新的转换过程中，数据寄存器中仍保持上一次的转换结果。0804提供两个信号输入端和，如果输入电压的变化范围从0V到，则芯片的端接地，输入电压加到端。对于差动输入，输入电压可以从非零开始，即到。此时端应接至等于的恒定电压上，而输入电压仍加到端上。0804转换器的零点无需调整，而输入电压的范围可以通过调整端处的电压加以改变。端电压应为输入电压的。例如输入电压范围是0V至2V，则在端应加1V，但当输入电压为0+5V时，端无需外加任何电压，而由内部电源分压得到。AD0804按图2-2和单片机相连时, 完成一次A/D采集的应用程序如下:AD0804: MOV P1, #0FFH ；对所有使用到I/O口置1 MOV P3, #0FFH CLR P3.0 ；选片及写信号置低，启动A/D CLR P3.6 NOP SETB P3.6 ；完成启动 SETB P3.0 WAIT: JNB P3.4, WAIT ；等待A/D结束信号 CLR P3.0 ；选片及读信号置低，发读信号 CLR P3.7 NOP MOV A, P1 ；取A/D结果送到A SETB P3.7 ；整个过程结束 SETB P3.0 RET68位D/A转换器DAC08321. 引脚及其功能DAC0832是双列直插式8位D/A转换器。能完成数字量输入到模拟量(电流)输出的转换。图1-1和图1-2分别为DAC0832的引脚图和内部结构图。其主要参数如下：分辨率为8位，转换时间为1s，满量程误差为1LSB，参考电压为(+10-10)V，供电电源为(+5+15)V，逻辑电平输入与TTL兼容。从图1-1中可见，在DAC0832中有两级锁存器，第一级锁存器称为输入寄存器，它的允许锁存信号为ILE，第二级锁存器称为DAC寄存器，它的锁存信号也称为通道控制信号 /XFER。图1-1、DAC0832引脚图图1-1中，当ILE为高电平，片选信号 /CS 和写信号 /WR1为低电平时，输入寄存器控制信号为1，这种情况下，输入寄存器的输出随输入而变化。此后，当 /WR1由低电平变高时，控制信号成为低电平，此时，数据被锁存到输入寄存器中，这样输入寄存器的输出端不再随外部数据DB的变化而变化。对第二级锁存来说，传送控制信号 /XFER 和写信号 /WR2同时为低电平时，二级锁存控制信号为高电平，8位的DAC寄存器的输出随输入而变化，此后，当 /WR2由低电平变高时，控制信号变为低电平，于是将输入寄存器的信息锁存到DAC寄存器中。图1-1中其余各引脚的功能定义如下：(1)、DI7DI0 ：8位的数据输入端，DI7为最高位。(2)、IOUT1 ：模拟电流输出端1，当DAC寄存器中数据全为1时，输出电流最大，当 DAC寄存器中数据全为0时，输出电流为0。(3)、IOUT2 ：模拟电流输出端2， IOUT2与IOUT1的和为一个常数，即IOUT1IOUT2常数。(4)、RFB ：反馈电阻引出端，DAC0832内部已经有反馈电阻，所以 RFB端可以直接接到外部运算放大器的输出端，这样相当于将一个反馈电阻接在运算放大器的输出端和输入端之间。(5)、VREF ：参考电压输入端，此端可接一个正电压，也可接一个负电压，它决定0至255的数字量转化出来的模拟量电压值的幅度，VREF范围为(+10-10)V。VREF端与D/A内部T形电阻网络相连。(6)、Vcc ：芯片供电电压，范围为(+5 15)V。(7)、AGND ：模拟量地，即模拟电路接地端。(8)、DGND ：数字量地。图1-2、DAC0832内部结构图2、 DAC0832的工作方式DAC0832可处于三种不同的工作方式：1、 直通方式 ：当ILE接高电平，、和都接数字地时，DAC处于直通方式，8位数字量一旦到达DI7DI0输入端，就立即加到8位D/A转换器，被转换成模拟量。例如在构成波形发生器的场合，就要用到这种方式，即把要产生基本波形的数据存在ROM中，连续取出送到DAC去转换成电压信号。2、 单缓冲方式 ：只要把两个寄存器中的任何一个接成直通方式，而用另一个锁存器数据，DAC就可处于单缓冲工作方式。一般的做法是将和都接地，使DAC寄存器处于直通方式，另外把ILE接高电平，接端口地址译码信号，接CPU的信号，这样就可以通过一条MOVX指令，选中该端口，使和有效，启动D/A转换。3、 双缓冲方式 ：主要在以下两种情况下需要用双缓冲方式的D/A转换。l 需在程序的控制下，先把转换的数据输入输入缓存器，然后在某个时刻再启动D/A转换。这样，可先选中端口，把数据写入输入寄存器；再选中端口，把输入寄存器内容写入DAC寄存器，实现D/A转换。l 在需要同步进行D/A转换的多路DAC系统中，采用双缓冲方式，可以在不同的时刻把要转换的数据打入各DAC的输入寄存器，然后由一个转换命令同时启动多个DAC转换。先用3条输出指令选择3个端口，分别将数据写入各DAC的输入寄存器，当数据准备就绪后，再执行一次写操作，使变低同时选通3个D/A的DAC寄存器，实现同步转换。3、DAC0832的应用图1-3为单片机和DAC0832直通方式输出连接图，运放输出电路输出电压为 UOUT(D/256)*VREF, 例如上图中向DAC0832传送的8位数据量40H(01000000B), 则输出电压UOUT=(64/256)*5V=1.25V，其输出过程可用MOV P1 , #40H一条指令完成。 图1-3、单片机和DAC0832直通方式输出连接图3DAC0830/DAC0832 8-Bit P Compatible, Double-Buffered D to A Converters General Description The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying DAC designed to interface directly with the 8080, 8048, 8085, Z80, and other popular microprocessors.Adeposited silicon-chromium R-2R resistor ladder network divides the reference current and provides the circuit with excellent tem- perature tracking characteristics (0.05% of Full Scale Range maximum linearity error over temperature). The circuit uses CMOS current switches and control logic to achieve low power consumption and low output leakage current errors. Special circuitry provides TTL logic input voltage level com- patibility. Double buffering allows these DACs to output a voltage cor- responding to one digital word while holding the next digital word. This permits the simultaneous updating of any number of DACs. The DAC0830 series are the 8-bit members of a family of microprocessor-compatible DACs (MICRO-DAC). Features n Double-buffered, single-buffered or flow-through digital data inputs n Easy interchange and pin-compatible with 12-bit DAC1230 series n Direct interface to all popular microprocessors n Linearity specified with zero and full scale adjust only NOT BEST STRAIGHT LINE FIT. n Works with10V reference-full 4-quadrant multiplication n Can be used in the voltage switching mode n Logic inputs which meet TTL voltage level specs (1.4V logic threshold) n Operates “STAND ALONE” (without P) if desired n Available in 20-pin small-outline or molded chip carrier package Key Specifications n Current settling time:1 s n Resolution:8 bits n Linearity:8, 9, or 10 bits (guaranteed over temp.) n Gain Tempco:0.0002% FS/C n Low power dissipation:20 mW n Single power supply:5 to 15 VDC Typical Application BI-FETand MICRO-DACare trademarks of National Semiconductor Corporation. Z80is a registered trademark of Zilog Corporation. DS005608-1 May 1999 DAC0830/DAC0832 8-Bit P Compatible, Double-Buffered D to A Converters 1999 National Semiconductor CorporationDS005608 Connection Diagrams(Top Views) Dual-In-Line and Small-Outline Packages DS005608-21 Molded Chip Carrier Package DS005608-22 2 Absolute Maximum Ratings(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC)17 VDC Voltage at Any Digital InputVCCto GND Voltage at VREFInput25V Storage Temperature Range65C to +150C Package Dissipation at TA=25C (Note 3)500 mW DC Voltage Applied to IOUT1or IOUT2(Note 4)100 mV to VCC ESD Susceptability (Note 4)800V Lead Temperature (Soldering, 10 sec.) Dual-In-Line Package (plastic)260C Dual-In-Line Package (ceramic)300C Surface Mount Package Vapor Phase (60 sec.)215C Infrared (15 sec.)220C Operating Conditions Temperature RangeTMINTATMAX Part numbers with “LCN” suffix0C to +70C Part numbers with “LCWM” suffix0C to +70C Part numbers with “LCV” suffix0C to +70C Part numbers with “LCJ” suffix40C to +85C Part numbers with “LJ” suffix55C to +125C Voltage at Any Digital InputVCCto GND Electrical Characteristics VREF=10.000 VDCunless otherwise noted. Boldface limits apply over temperature, TMINTATMAX. For all other limits TA =25C. ParameterConditions See Note VCC= 4.75 VDC VCC= 15.75 VDC VCC = 5 V DC5% VCC = 12 V DC5% to 15 VDC5% Limit Units Typ (Note 12) Tested Limit (Note 5) Design Limit (Note 6) CONVERTER CHARACTERISTICS Resolution888bits Linearity Error MaxZero and full scale adjusted4, 8 10VVREF+10V DAC0830LJ WR2 and XFER GROUNDED FIGURE 4. 10 DAC0830 Series Application Hints(Continued) 2.0 ANALOG CONSIDERATIONS The fundamental purpose of any D to A converter is to pro- vide an accurate analog output quantity which is representa- tive of the applied digital word. In the case of the DAC0830, the output, IOUT1, is a current directly proportional to the product of the applied reference voltage and the digital input word. For application versatility, a second output, IOUT2, is provided as a current directly proportional to the complement of the digital input. Basically: where the digital input is the decimal (base 10) equivalent of the applied 8-bit binary word (0 to 255), VREFis the voltage at pin 8 and 15 k is the nominal value of the internal resis- tance, R, of the R-2R ladder network (discussed in Section 2.1). Several factors external to the DAC itself must be consid- ered to maintain analog accuracy and are covered in subse- quent sections. 2.1 The Current Switching R-2R Ladder The analog circuitry,Figure 6, consists of a silicon-chromium (SiCr or Si-chrome) thin film R-2R ladder which is deposited on the surface oxide of the monolithic chip. As a result, there are no parasitic diode problems with the ladder (as there may be with diffused resistors) so the reference voltage, VREF, can range 10V to +10V even if VCCfor the device is 5VDC. The digital input code to the DAC simply controls the position of the SPDT current switches and steers the available ladder current to either IOUT1or IOUT2as determined by the logic in- put level (“1” or “0”) respectively, as shown inFigure 6. The MOS switches operate in the current mode with a small volt- age drop across them and can therefore switch currents of either polarity. This is the basis for the 4-quadrant multiplying feature of this DAC. 2.2 Basic Unipolar Output Voltage To maintain linearity of output current with changes in the ap- plied digital code, it is important that the voltages at both of the current output pins be as near ground potential (0VDC) as possible. With VREF=+10V every millivolt appearing at ei- ther IOUT1or IOUT2will cause a 0.01% linearity error. In most applications this output current is converted to a voltage by using an op amp as shown inFigure 7. The inverting input of the op amp is a “virtual ground” created by the feedback from its output through the internal 15 k re- sistor, Rfb. All of the output current (determined by the digital input and the reference voltage) will flow through Rfbto the output of the amplifier. Two-quadrant operation can be ob- tained by reversing the polarity of VREFthus causing IOUT1to flow into the DAC and be sourced from the output of the am- plifier. The output voltage, in either case, is always equal to IOUT1xRfband is the opposite polarity of the reference volt- age. The reference can be either a stable DC voltage source or an AC signal anywhere in the range from 10V to +10V. The DAC can be thought of as a digitally controlled attenuator: the output voltage is always less than or equal to the applied reference voltage. The VREFterminal of the device presents a nominal impedance of 15 k to ground to external circuitry. Always use the internal Rfbresistor to create an output volt- age since this resistor matches (and tracks with tempera- ture) the value of the resistors used to generate the output current (IOUT1). DS005608-8 FIGURE 5. Accommodating a High Speed System 11 DAC0830 Series Application Hints(Continued) 2.3 Op Amp Considerations The op amp used inFigure 7should have offset voltage null- ing capability (See Section 2.5). The selected op amp should have as low a value of input bias current as possible. The product of the bias current times the feedback resistance creates an output voltage er- ror which can be significant in low reference voltage applica- tions. BI-FETop amps are highly recommended for use with these DACs because of their very low input current. Transient response and settling time of the op amp are im- portant in fast data throughput applications. The largest sta- bility problem is the feedback pole created by the feedback resistance, Rfb, and the output capacitance of the DAC. This appears from the op amp output to the () input and includes the stray capacitance at this node. Addition of a lead capaci- tance, CCinFigure 8, greatly reduces overshoot and ringing at the output for a step change in DAC output current. Finally, the output voltage swing of the amplifier must be greater than VREFto allow reaching the full scale output volt- age. Depending on the loading on the output of the amplifier and the available op amp supply voltages (only12 volts in many development systems), a reference voltage less than 10 volts may be necessary to obtain the full analog output voltage range. 2.4 Bipolar Output Voltage with a Fixed Reference The addition of a second op amp to the previous circuitry can be used to generate a bipolar output voltage from a fixed ref- erence voltage. This, in effect, gives sign significance to the MSB of the digital input word and allows two-quadrant multi- plication of the reference voltage. The polarity of the refer- ence can also be reversed to realize full 4-quadrant multipli- cation:VREFxDigital Code=VOUT. This circuit is shown inFigure 9. This configuration features several improvements over exist- ing circuits for bipolar outputs with other multiplying DACs. Only the offset voltage of amplifier 1 has to be nulled to pre- serve linearity of the DAC. The offset voltage error of the second op amp (although a constant output voltage error) has no effect on linearity. It should be nulled only if absolute output accuracy is required. Finally, the values of the resis- tors around the second amplifier do not have to match the in- ternal DAC resistors, they need only to match and tempera- ture track each other. A thin film 4-resistor network available from Beckman Instruments, Inc. (part no. 694-3-R10K-D) is ideally suited for this application. These resistors are matched to 0.1% and exhibit only 5 ppm/C resistance track- ing temperature coefficient. Two of the four available 10 k resistors can be paralleled to form R inFigure 9and the other two can be used independently as the resistances la- beled 2R. 2.5 Zero Adjustment For accurate conversions, the input offset voltage of the out- put amplifier must always be nulled. Amplifier offset errors create an overall degradation of DAC linearity. The fundamental purpose of zeroing is to make the voltage appearing at the DAC outputs as near 0VDCas possible. This is accomplished for the typical DAC op amp connec- tion (Figure 7) by shorting out Rfb, the amplifier feedback re- sistor, and adjusting the VOSnulling potentiometer of the op amp until the output reads zero volts. This is done, of course, with an applied digital code of all zeros if IOUT1is driving the op amp (all ones for IOUT2). The short around Rfbis then re- moved and the converter is zero adjusted. DS005608-37 FIGURE 6. DS005608-38 FIGURE 7. 12 DAC0830 Series Application Hints(Continued) 2.6 Full-Scale Adjustment In the case where the matching of Rfbto the R value of the R-2R ladder (typically0.2%) is insufficient for full-scale ac- curacy in a particular application, the VREFvoltage can be adjusted or an external resistor and potentiometer can be added as shown inFigure 10to provide a full-scale adjust- ment. The temperature coefficients of the resistors used for this ad- justment are of an important concern. To prevent degrada- tion of the gain error temperature coefficient by the external resistors, their temperature coefficients ideally would have to match that of the internal DAC resistors, which is a highly im- practical constraint. For the values shown inFigure 10, if the resistor and the potentiometer each had a temperature coef- ficient of100 ppm/C maximum, the overall gain error tem- perature coefficent would be degraded a maximum of 0.0025%/C for an adjustment pot setting of less than 3% of Rfb. DS005608-39 ts OP AmpCC(O to Full Scale) LF35622 pF4 s LF35122 pF5 s LF357*10 pF2 s *2.4 k RESISTOR ADDED FROMINPUT TO GROUND TO INSURE STABILITY FIGURE 8. DS005608-40 Input CodeIDEAL VOUT MSBLSB+VREFVREF 11111111 11000000 10000000 01111111 00111111 00000000 *THESE RESISTORS ARE AVAILABLE FROM BECKMAN INSTRUMENTS, INC. AS THEIR PART NO. 694-3-R10K-D FIGURE 9. 13 DAC0830 Series Application Hints (Continued) 2.7 Using the DAC0830 in a Voltage Switching Configuration The R-2R ladder can also be operated as a voltage switch- ing network. In this mode the ladder is used in an inverted manner from the standard current switching configuration. The reference voltage is connected to one of the current out- put terminals (IOUT1for true binary digital control, IOUT2is for complementary binary) and the output voltage is taken from the normal VREFpin. The converter output is now a voltage in the range from 0V to 255/256 VREFas a function of the ap- plied digital code as shown inFigure 11. This configuration offers several useful application advan- tages. Since the output is a voltage, an external op amp is not necessarily required but the output impedance of the DAC is fairly high (equal to the specified reference input re- sistance of 10 k to 20 k) so an op amp may be used for buffering purposes. Some of the advantages of this mode are illustrated inFigures 12, 13, 14, 15. There are two important things to keep in mind when using this DAC in the voltage switching mode. The applied refer- ence voltage must be positive since there are internal para- sitic diodes from ground to the IOUT1and IOUT2terminals which would turn on if the applied reference went negative. There is also a dependence of conversion linearity and gain error on the voltage difference between VCCand the voltage applied to the normal current output terminals. This is a re- sult of the voltage drive requirements of the ladder switches. To ensure that all 8 switches turn on sufficiently (so as not to add significant resistance to any leg of the ladder and thereby introduce additional linearity and gain errors) it is recommended that the applied reference voltage be kept less than +5VDCand VCCbe at least 9V more positive than VREF. These restrictions ensure less than 0.1% linearity and gain error change.Figures 16, 17, 18characterize the ef- fects of bringing VREFand VCCcloser together as well as typical temperature performance of this voltage switching configuration. DS005608-11 FIGURE 10. Adding Full-Scale Adjustment DS005608-12 FIGURE 11. Voltage Mode Switching DS005608-41 Voltage switching mode eliminates output signal inver- sion and therefore a need for a negative power supply. Zero code output voltage is limited by the low level output saturation voltage of the op amp. The 2 k pull-down re- sistor helps to reduce this voltage. VOSof the op amp has no effect on DAC linearity. FIGURE 12. Single Supply DAC 14 DAC0830 Series Application Hints(Continued) DS005608-42 FIGURE 13. Obtaining a Bipolar Output from a Fixed Reference with a Single Op Amp DS005608-60 FIGURE 14. Bipolar Output with Increased Output Voltage Swing 15 DAC0830 Series Application Hints(Continued) DS005608-14 FIGURE 15. Single Supply DAC with Level Shift and Span- Adjustable Output Gain and Linearity Error Variation vs. Supply Voltage DS005608-32 Note: For these curves, VREFis the voltage applied to pin 11 (IOUT1) with pin 12 (IOUT2) grounded. FIGURE 16. Gain and Linearity Error Variation vs. Reference Voltage DS005608-33 FIGURE 17. 16 DAC0830 Series Application Hints (Continued) 2.8 Miscellaneous Application Hints These converters are CMOS products and reasonable care should be exercised in handling them to prevent catastrophic failures due to static discharge. Conversion accuracy is only as good as the applied refer- ence voltage so providing a stable source over time and tem- perature changes is an important factor to consider. A “good” ground is most desirable. A single point ground dis- tribution technique for analog signals and supply returns keeps other devices in a system from affecting the output of the DACs. During power-up supply voltage sequencing, the 15V (or 12V) supply of the op amp may appear first. This will cause the output of the op amp to bias near the negative supply po- tential. No harm is done to the DAC, however, as the on-chip 15 k feedback resistor sufficiently limits the current flow from IOUT1when this lead is internally clamped to one diode drop below ground. Careful circuit construction with minimization of lead lengths around the analog circuitry, is a primary concern. Good high frequency supply decoupling will aid in preventing inadvert- ant noise from appearing on the analog output. Overall noise reduction and reference stability is of particular concern when using the higher accuracy versions, the DAC0830 and DAC0831, or their advantages are wasted. 3.0 GENERAL APPLICATION IDEAS The connections for the control pins of the digital input regis- ters are purposely omitted. Any of the control formats dis- cussed in Section 1 of the accompanying text will work with any of the circuits shown. The method used depends on the overall system provisions and requirements. The digital input code is referred to as D and represents the decimal equivalent value of the 8-bit binary input, for ex- ample: Binary InputD Pin 13Pin 7Decimal MSBLSBEquivalent 11111111255 10000000128 0001000016 000000102 000000000 Gain and Linearity Error Variation vs. Temperature DS005608-34 FIGURE 18. 17 Applications DAC Controlled Amplifier (Volume Control) DS005608-43 Capacitance Multiplier DS005608-44 Variable fO, Variable