Verilog HDL 四位移位乘法器.doc

实验五四位移位乘法器一、 实验代码：（led显示）module mult(mul,a,b); output 7:0 mul;/input ckl;input 3:0 a,b;reg 7:0 mul;wire 3:0 out1,out2,out3,out4;/wire 3:0 out2;/wire 3:0 out3;/wire 3:0 out4;/如果always快里有问题，用clk进行延时接受，确保无问题reg 7:0 temp=8b0;reg 7:0 temp_mul=8b0;multply cheng1(out1,a,b3);multply cheng2(out2,a,b2);multply cheng3(out3,a,b1);multply cheng4(out4,a,b0); always (a or b)begintemp=4b0,out1;temp_mul=temp1;temp=4b0,out2;temp_mul=temp_mul+temp;temp_mul=temp_mul1;temp=4b0,out3;temp_mul=temp_mul+temp;temp_mul=temp_mul1;temp=4b0,out4;mul=temp_mul+temp;endendmodulemodule multply(out,mul4,mul1);output 3:0 out;input 3:0 mul4;input mul1;reg 3:0 out;reg 3:0 tem;always (mul4 or mul1)begincase(mul1)1b0:tem=4b0;default: tem=mul4&4b1111;endcaseout=tem;endendmodule二、 管脚配置：通过拨动输入：a0 input PIN_200a1 input PIN_202a2 input PIN_203a3 input PIN_204b0 input PIN_205b1 input PIN_206b2 input PIN_207b3 input PIN_208led灯输出：mul0 output PIN_191mul1 output PIN_192mul2 output PIN_193mul3 output PIN_195mul4 output PIN_196mul5 output PIN_197mul6 output PIN_198mul7 output PIN_199三、 实验连线：通过拨动输入：K1-K8:11-18 Led灯显示连线：L1-L8:3-10四、 电路工作原理手动拨动，开关k1-k8，根据Led灯的显示，亮表示1，不亮表示0来看结果。五、 实验问题当用八段译码显示管，利用十六进制来表示结果时，遇到一些问题，无法操作成功。总是要么同时选通但只显示一个，要么就是只选通一个。八段译码显示管显示：module mult(mul,outa,outb,a,b,clk); output 7:0 mul;output outa,outb;input clk;input 3:0 a,b;reg outa;reg outb;reg 7:0 mul;reg te;wire 3:0 out1,out2,out3,out4;reg 7:0 temp=8b0;reg 7:0 temp_mul=8b0;multply cheng1(out1,a,b3);multply cheng2(out2,a,b2);multply cheng3(out3,a,b1);multply cheng4(out4,a,b0); /*always(posedge clk)begin if(te=0) begin outb=outb; outa=outa; te=te+1; endendalways(posedge clk)begin if(te=30)begin outa=outb; outb=outb; te=te+1; endelse if(te=60)begin outb=outa; outa=outa; te=0; endelsebegin te=te+1; endend*/always(posedge clk)beginif(te256) te=te+1;else begin te=0; outb=outa; outa=outa; outb=outb;endendalways (a or b)begintemp=4b0,out1;temp_mul=temp1;temp=4b0,out2;temp_mul=temp_mul+temp;temp_mul=temp_mul1;temp=4b0,out3;temp_mul=temp_mul+temp;temp_mul=temp_mul1;temp=4b0,out4;temp_mul=temp_mul+temp;endalways(posedge clk)beginif(outa=0&outb=1)begincase(temp_mul3:0)4h0: mul= 8h03;/显示04h1: mul = 8h9f;/显示14h2: mul = 8h25;/显示24h3: mul= 8h0d;/显示34h4: mul = 8h99;/显示44h5: mul = 8h49;/显示54h6: mul = 8h41;/显示64h7: mul = 8h1f;/显示74h8: mul = 8h01;/显示84h9: mul = 8h09;/显示94ha: mul = 8h11;/显示A4hb: mul = 8h01;/显示B4hc: mul = 8h63;/显示C4hd: mul = 8h03;/显示D4he: mul = 8h61;/显示E4hf: mul = 8h71;/显示Fdefault: ;endcaseendelse if(outb=0&outa=1)begincase(temp_mul7:4)4h0: mul = 8h03;/显示04h1: mul = 8h9f;/显示14h2: mul = 8h25;/显示24h3: mul = 8h0d;/显示34h4: mul = 8h99;/显示44h5: mul = 8h49;/显示54h6: mul = 8h41;/显示64h7: mul = 8h1f;/显示74h8: mul = 8h01;/显示84h9: mul = 8h09;/显示94ha: mul = 8h11;/显示A4hb: mul = 8h01;/显示B4hc: mul = 8h63;/显示C4hd: mul = 8h03;/显示D4he: mul = 8h61;/显示E4hf: mul = 8h71;/显示Fdefault: ;endcaseendelsemul = 8h03;endendmodulemodule multply(out,mul4,mul1);output 3:0 out;input 3:0 mul4;input mul1;reg 3:0 out;reg 3:0 tem;always (mul4 or mul1)begincase(mul1)1b0:tem=4b0;default: tem=mul4&4b1111;endcaseout=tem;endendmodule八段连线问题：a0 input PIN_86a1 input PIN_87a2 input PIN_88a3 input PIN_89b0 input PIN_90b1 input PIN_92b2 input PIN_93b3 input PIN_94clk input PIN_191outa output 83outb output 85mul0 output PIN_200mu