超大规模集成电路设计导论(VLSI)总复习(全英).docx

VLSI复习题型：缩写 5题 10分简答 12题 60分计算 3题 30分缩写英文中文VLSIVery large scale integration超大规模集成VTCVoltage transfer characteristic电压传输特性PTPass-Transistor传输管TGTransmission Gate传输门CPL/DPLDifferential Pass-transistor Logic差分传输管逻辑MSMaster-Slave主从ETEdge-Triggered边沿触发CMOSComplementary metal oxide semiconductor互补型金属氧化物半导体管NoCOn-Chip Network片上网络SoCSystem on Chip片上系统IPIntellectual Property专利GAGate Array门阵列FPGAField-Programmable Gate Array现场可编程门阵列PLAProgrammable Logic Array可编程逻辑阵列PLDProgrammable Logic Device可编程逻辑器件PALProgrammable Array Logic Device可编程阵列逻辑器件LUTLook-up Table查表FAMOSFloating-gate transistor(metal oxide semiconductor)浮栅晶体管S/DRAMStatic/Dynamic Random Access Memory静/动态可读写存储器RWMRead-write memory读写存储器ATDAddress Transition Detection地址翻转探测DFTDesign-for-test可侧性设计DUTDevice under test被测器件BISTBuilt in self test内建自测试EDAElectronic Design Automation电子设计自动化TSPCRTrue Single-Phase Clocked Tegister真单相钟控寄存器Chapter 011. Howtoevaluateperformance Cost Reliability Speed(delay,operatingfrequency) Powerdissipation2. Regenerative property3. Delay :Chapter 021. Inverter layout2. Photolithography process1) Oxidation layering(氧化层)2) Pthotoresist coating（涂光刻胶）3) Stepper exposure（光刻机曝光）4) Photoresist development and bake(光刻胶的显影和烘干)5) Acid etching（酸刻蚀）6) Spin, rinse, and dry（旋转，清洗和干燥）7) Various process steps：Ionimplantation（离子注入）Plasmaetching（等离子刻蚀）Metaldeposition（金属沉淀）8) Photoresist removal( or ashing) 去除光刻胶（即“沙洗”）Chapter 031. Linear/ Saturation mode2. Long channel vs short channel 3. Capacitances= structure capacitances+channel capacitances+MOS diffusion capacitances4. Resistance=MOS sructure resistance+source and drain resistance+cantact resistance+wiring resistanceWithsilicidation R方块 isreducedtotherange1to4/方块（source and drain resistance）Chapter 041. Cwire =Cpp +Cfringe +Cinterwire2. Dealing with resistance:1) Use better interconnect materials2) More interconnect layers3. RC Mode LumpedRCmodel totalwireresistanceislumpedintoasingleRandtotalcapacitanceintoasingleC goodforshortwires;pessimisticandinaccurateforlongwires DistributedRCmodel circuitparasitics aredistributed alongthelength,L,ofthewire4. Delay Delayofawireisaquadratic functionofitslength,LThedelayis1/2ofthatpredicted(bythelumpedmodel)5. Reflection coefficient 【画传输图（or 波形），计算题】Chapter 051. VM(W/L)p/(W/L)n IncreasingthewidthofthePMOSmovesVM towardsVDD, Increasingthewidthofthe NMOSmovesVM towardsGND.2. Delay 3. PowerinCMOS1. Dynamic power consumption: charging and discharging capacitors; Not a function of transistor sizes; Need to reduce CL,Vdd,and f to reduce power.2. Short circuit currents: short circuit path supply rails during switching; Keep the input and output rise/fall times the same;If VddVtn+|Vtp|,then short-circuit power can be eliminated.3. Leakage: leaking diodes and transistors4. Technology scaling modelsFull scalingFixed voltage scalingGeneral scalingChapter 061. Static CMOS- output connected to either Vdd or GND via a low-resistance pathn High noise marginsn Low output impedance, high input impedancen No steady state path between Vdd and GNDn Delay is a function of load capacitance and transistor resistanceDynamic CMOS-relies on temporary storage of signal values on capacitance of high-impedance circuit nodes.n Simpler, faster gatesn Increased sensitivity to noise2. Static vs dynamic circuitn In static circuit at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. -fan-in of N requires 2N devicesn Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes-requires only N+2 transistors-takes a sequence of precharge and conditional evaluation phases to realize logic functions.l conditions on output1) once the optput of a dynamic gate is discharged, it cannot be charged again until the next precharge opreation.2) Inputs to the gate can make at most one transition during evaluation.3) Output can be in the high impedance state during and after evaluation(PDN off), state is stored in CL.l PropertiesofDynamicGates1) LogicfunctionisimplementedbythePDNonly numberoftransistorsisN+2(versus2NforstaticcomplementaryCMOS) shouldbesmallerinareathanstaticcomplementaryCMOS2) Fullswingoutputs(VOL =GNDandVOH =VDD)3) Nonratioed-sizingofthedevicesisnotimportantforproperfunctioning(onlyforperformance)4) Fasterswitchingspeeds5) Powerdissipationshouldbebetter- consumesonlydynamicpowernoshortcircuitpowerconsumptionsincethepull- uppathisnotonwhenevaluating- lowerCL-bothCint(sincetherearefewertransistorsconnectedtothedrainoutput)andCext (sincetheretheoutputloadisoneperconnected gate,nottwo)- byconstructioncanhaveatmostonetransitionpercycle noglitching 6) Needs a percharge clock3. Combinational vs Sequential logic4. Why PMOS in PUN and NMOS in PDN?Threshold drops5. Ratioed logic: Pseudo-NMOSSmall area and load, but static power dissipationChapter 071. Latch vs Registern Latch: level sensitive-As for positive: passes inputs to Q when the clock is high-transparent mode; When clock is low-hold moden Flip-flop: edge sensitive2. Bistable circuit:Thecross couplingoftwoinvertersresultsinabistablecircuit(acircuitwithtwostablestates)n Have to be able to change the stored value by making A (or B) temporarily unstable by increasing the loop gain to a value larger than 1 Done by applying a trigger pulse at Vi1 or Vi2the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter)n Two approaches used1. cutting the feedback loop (mux based latch)2. overpowering the feedback loop (as used in SRAMs)3. MS ET timing propertiesn Set-up time: time before rising edge of clk that D must be validn Propagation delay: time for QM to reach Qn Hold time: time D must be stable after rising edge of clk4. Pipelining 5. Schmitt Trigger(riseP; fallN)Chapter 091. Cross Talk: An unwanted coupling from a neighboring signal wire to a network node introduces an interference that is generally called cross talk. 2. DealingwithCapacitiveCrossTalk Avoidfloatingnodes Protectsensitivenodes Makeriseandfalltimesaslargeaspossible Differentialsignaling Donotrunwirestogetherforalongdistance Useshieldingwires Useshieldinglayers3. Cross Talk and Performance: when neighboring lines switch in opposite direction of victim line, delay increases. 4. Impactofresistanceiscommonlyseeninpowersupplydistribution: IRdrop VoltagevariationsChapter 101. Clock Nonidealities:n Clock skew: Spatial variation in temporally equivalent clock edges;n Clock jitter: Temporal variations in consecutive edges of the clock signaln Variation of the pulse width2. Clock Uncertainties-Source of clock uncertainty（图形填空）（重点）简答题： ClockSignalGeneration(1) ManufacturingDeviceVariations(2) InterconnectVariations(3) EnvironmentalVariations(4and5) CapacitiveCoupling(6and7)3. Impact of Positive/Negative Clock Skew and Clock jitter (重点)1. Positive clock skew:Clock and data flow in the same direction2. Negative clock skew: Clock and data flow in opposite directions3. Jitter cause T to vary on a cycle-by-cycle basisCombined impact of skew and jitter:Constraints on the minimum clock period (positive)4.To reduce dynamic power, the clock network must support clock gating (shutting down(disabling the clock ) units)5. Clock distribution techniques-Balanced paths(H-tree network, matched RC trees)-Clock grids: minimize absolute delay6.Matched RC trees, represents a floor plan that distributes the clock signal so that the interconnections carrying the clock signals to the functional subblocks are of equal length.7. 彩图9：The unbalanced load creates a large skew, by careful tuning of the wire width, the load is balanced, minimizing the skew. 8. DealingwithClockSkewandJitterTominimizeskew,balanceclockpathsusingH-treeormatched-tree clockdistributionstructures. Ifpossible,routedataandclockinoppositedirections;eliminatesracesatthecostofperformance. Theuseofgatedclockstohelpwithdynamicpowerconsumptionmakejitterworse. Shieldclockwires(routepowerlinesVDD orGNDnexttoclocklines)tominimize/eliminatecouplingwithneighboringsignalnets. Usedummyfillstoreduceskewbyreducingvariationsininterconnectcapacitancesduetointerlayerdielectricthicknessvariations. Bewareoftemperatureandsupplyrailvariationsandtheireffectsonskewandjitter. Powersupplynoisefundamentallylimitstheperformanceofclo