msp430g2553定时器A.doc

Chapter 12SLAU144IDecember 2004Revised January 2012Timer_ATimer_A is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes theoperation of the Timer_A of the MSP430x2xx device family.Topic . Page12.1 Timer_A Introduction . 36412.2 Timer_A Operation . 36512.3 Timer_A Registers . 377第12章SLAU144I 2004年12月2012年1月修订定时器A定时器A是与多个捕获/比较寄存器的16位定时器/计数器。本章介绍MSP430x2xx器件系列定时器A的操作。主题页12.1定时器A介绍. . 36412.2定时器A的操作. . 36512.3定时器A寄存器. . 37712.1 Timer_A IntroductionTimer_A is a 16-bit timer/counter with three capture/compare registers. Timer_A can support multiplecapture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of thecapture/compare registers.12.1定时器A简介定时器A是一个16位定时器/柜台三个捕捉/比较寄存器。定时器A可以支持多个捕捉/比较PWM输出，间隔的时间。定时器A还拥有丰富的中断功能。从计数器溢出条件，并从每个可能会产生中断捕捉/比较寄存器。Timer_A features include:定时器A的功能包括： Asynchronous 16-bit timer/counter with four operating modes Selectable and configurable clock source Two or three configurable capture/compare registers Configurable outputs with PWM capability Asynchronous input and output latching Interrupt vector register for fast decoding of all Timer_A interrupts异步16位定时器/计数器四种工作模式可选择的和可配置的时钟源两个或三个可配置的捕捉/比较寄存器可配置的输出PWM功能异步输入和输出锁存快速解码的所有定时器A中断的中断向量寄存器The block diagram of Timer_A is shown in Figure 12-1.（定时器A的框图如图12-1所示）NOTE: Use of the Word CountCount is used throughout this chapter. It means the counter must be in the process ofcounting for the action to take place. If a particular value is directly written to the counter,then an associated action will not take place.注意：使用的字数注意： 使用的单词计数在本章中使用计数。这意味着该计数器的过程中必须是计数为采取的行动。如果一个特定的值直接写入计数器，然后执行相应的操作不会发生。12.2 Timer_A Operation（12.2定时器A操作）The Timer_A module is configured with user software. The setup and operation of Timer_A is discussed inthe following sections.定时器A模块与用户软件配置。定时器A的设置和操作进行了讨论以下各节12.2.1 16-Bit Timer Counter（12.2.1 16位定时器计数器）The 16-bit timer/counter register, TAR, increments or decrements (depending on mode of operation) witheach rising edge of the clock signal. TAR can be read or written with software. Additionally, the timer cangenerate an interrupt when it overflows16位定时器/计数器寄存器，焦油，递增或递减（取决于操作模式）每个时钟信号的上升沿。西藏自治区可以阅读或编写的软件。此外，定时器可以溢出时产生中断TAR may be cleared by setting the TACLR bit. Setting TACLR also clears the clock divider and countdirection for up/down mode.TAR 可清除设置TACLR位。设置TACLR也清除时钟分频器和计数方向向上/向下模式。定时器A操作NOTE: Modifying Timer_A Registers(注：修改定时器A寄存器)It is recommended to stop the timer before modifying its operation (with exception of theinterrupt enable, and interrupt flag) to avoid errant operating conditions.建议之前停止修改其运作的定时器（与例外中断使能，中断标志） ，以避免犯错误的操作。When the timer clock is asynchronous to the CPU clock, any read from TAR should occurwhile the timer is not operating or the results may be unpredictable. Alternatively, the timermay be read multiple times while operating, and a majority vote taken in software todetermine the correct reading. Any write to TAR will take effect immediately.当定时器的时钟是异步的CPU时钟，读任何从西藏自治区应该发生当定时器不工作或可能是不可预知的结果。另外，定时器可多次读取操作时，多数票软件采取确定正确的读数。任何写入到西藏自治区将立即生效。 Clock Source Select and Divider（时钟源选择和分频）The timer clock can be sourced from ACLK, SMCLK, or externally via TACLK or INCLK. The clock sourceis selected with the TASSELx bits. The selected clock source may be passed directly to the timer or divided by 2, 4, or 8, using the IDx bits. The timer clock divider is reset when TACLR is set.定时器的时钟可以来源于ACLK ， SMCLK ，或外部，通过TACLK或INCLK 。时钟源被选中与TASSELx位。选定的时钟源可以直接传递到计时器或除以2，4，或8个使用IDX位。定时器时钟分频器复位设置TACLR时12.2.2 Starting the Timer（12.2.2启动定时器）The timer may be started, or restarted in the following ways: 计时器可以启动，或重新在以下方面：The timer counts when MCx 0 and the clock source is active. 定时器计数时MCX 0和时钟源是积极的。 When the timer mode is either up or up/down, the timer may be stopped by writing 0 to TACCR0. Thetimer may then be restarted by writing a nonzero value to TACCR0. In this scenario, the timer starts incrementing in the up direction from zero.当定时器模式是向上或向上/向下，定时器可以通过写0到TACCR0停止。 “写一个非零值TACCR0 ，然后重新启动定时器。在这种情况下，定时器启动从零向上的方向递增。12.2.3 Timer Mode Control（12.2.3定时器模式控制）The timer has four modes of operation as described in Table 12-1: stop, up, continuous, and up/down.The operating mode is selected with the MCx bits.计时器有四种操作模式，如表12-1中所述：停止，最多，持续，向上/向下。操作模式选择与MCX位。 Table 12-1. Timer Modes表12-1 。定时器模式MCx Mode模式 Description描述00 Stop The timer is halted00停止计时器停止01 Up The timer repeatedly counts from zero to the value of TACCR0. 01多次了定时器计数从零的TACCR0的价值 10 Continuous The timer repeatedly counts from zero to 0FFFFh.10连续计时器反复计算从零到0FFFFH 11 Up/down The timer repeatedly counts from zero up to the value of TACCR0 and back down to zero.11向上/向下定时器反复计数从零到价值TACCR0回落到零。 Up Mode(增加模式)The up mode is used if the timer period must be different from 0FFFFh counts. The timer repeatedlycounts up to the value of compare register TACCR0, which defines the period, as shown in Figure 12-2.The number of timer counts in the period is TACCR0+1. When the timer value equals TACCR0 the timerrestarts counting from zero. If up mode is selected when the timer value is greater than TACCR0, thetimer immediately restarts counting from zero.使用定时器的周期必须0FFFFH计数不同模式。计时器反复计数比较寄存器TACCR0 ，它定义期间的价值，在图12-2所示。定时器计数期间是TACCR0 +1 。当定时器的值等于TACCR0定时器从零重新开始计数。如果选择启动模式时，计时器值是比TACCR0大，计时器立即重新启动从零计数。 图12-2 。启动模式The TACCR0 CCIFG interrupt flag is set when the timer counts to the TACCR0 value. The TAIFG interrupt flag is set when the timer counts from TACCR0 to zero. Figure 12-3 shows the flag set cycle.中断标志TACCR0 CCIFG时设置的定时器计数的TACCR0价值。在TAIFG中断标志被设置时，定时器计数从TACCR0零。图12-3显示了标志设置周期。 Changing the Period Register TACCR0（改变的时期注册TACCR0）When changing TACCR0 while the timer is running, if the new period is greater than or equal to the oldperiod, or greater than the current count value, the timer counts up to the new period. If the new period isless than the current count value, the timer rolls to zero. However, one additional count may occur before the counter rolls to zero当改变TACCR0定时器运行时，如果新的时期是大于或等于旧期间，或大于当前计数值，计数到新的时期。如果新的时期是小于当前值，定时滚动到零。然而，一个额外的数量才可能发生计数器为零辊 Continuous ModeIn the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts from zero as shown inFigure 12-4. The capture/compare register TACCR0 works the same way as the other capture/compare registers.在连续模式下，定时器反复计算了从零到0FFFFH并重新启动所示图12-4。捕获/比较寄存器TACCR0工程以同样的方式，其他的捕获/比较寄存器。The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero. Figure 12-5 shows the flag set cycle.TAIFG中断标志时设置定时器计数从0FFFFH至零。图12-5显示了标志设置周期。 图12-5 。连续模式标志设置 Use of the Continuous Mode（使用连续模式）The continuous mode can be used to generate independent time intervals and output frequencies. Eachtime an interval is completed, an interrupt is generated. The next time interval is added to the TACCRxregister in the interrupt service routine. Figure 12-6 shows two separate time intervals t0 and t1 beingadded to the capture/compare registers. In this usage, the time interval is controlled by hardware, notsoftware, without impact from interrupt latency. Up to three independent time intervals or outputfrequencies can be generated using all three capture/compare registers.连续模式可用于生成独立的时间间隔和输出频率。每时间的间隔完成后，会产生一个中断。在未来的时间间隔添加的TACCRx在中断服务程序的注册。图12-6显示了两个不同的时间间隔T0和T1是添加到捕获/比较寄存器。在这种用法中，由硬件控制的时间间隔，而不是软件，没有中断延迟的影响。三个独立的时间间隔或输出使用所有三个捕捉/比较寄存器可以产生频率。 【定时器A操作】 图12-6 。连续模式下的时间间隔Time intervals can be produced with other modes as well, where TACCR0 is used as the period register.Their handling is more complex since the sum of the old TACCRx data and the new period can be higherthan the TACCR0 value. When the previous TACCRx value plus tx is greater than the TACCR0 data, TACCR0 + 1 must be subtracted to obtain the correct time interval.时间间隔可以生产以及其他交通工具，其中TACCR0使用周期寄存器。他们的处理是比较复杂的的老TACCRx数据和新的时期以来的总和可以更高比TACCR0值。当以前TACCRx值加TX比TACCR0数据更大，TACCR0 + 1必须减去获得正确的时间间隔。 Up/Down ModeThe up/down mode is used if the timer period must be different from 0FFFFh counts, and if a symmetricalpulse generation is needed. The timer repeatedly counts up to the value of compare register TACCR0 andback down to zero, as shown in Figure 12-7. The period is twice the value in TACCR0.使用向上/向下模式，如果定时器的周期必须从0FFFFH计数不同，如果一个对称脉冲的产生是必要的。计时器反复计算值和比较寄存器TACCR0回落到零，如图12-7所示。期间的两倍值在TACCR0 。The count direction is latched. This allows the timer to be stopped and then restarted in the same directionit was counting before it was stopped. If this is not desired, the TACLR bit must be set to clear the direction. The TACLR bit also clears the TAR value and the timer clock divider被锁定的计数方向。这使得定时器被停止，并且在同一个方向，然后重新启动它计数，然后才停止。如果这是不理想， TACLR位必须设置以清除方向。 TACLR位也清除西藏自治区价值和定时器时钟分频器In up/down mode, the TACCR0 CCIFG interrupt flag and the TAIFG interrupt flag are set only once duringa period, separated by 1/2 the timer period. The TACCR0 CCIFG interrupt flag is set when the timercounts from TACCR0 1 to TACCR0, and TAIFG is set when the timer completes counting down from 0001h to 0000h. Figure 12-8 shows the flag set cycle.在向上/向下模式， TACCR0 CCIFG中断国旗和TAIFG的中断标志设置只有一次一段时间，由1/2定时器的周期分隔。 TACCR0 CCIFG中断标志当定时器设置从TACCR0计数 - 1至TACCR0 ，并TAIFG的设置时，计时器完成倒计时0001H到0000H 。图12-8显示了标志设置的周期 图12-8 。向上/向下模式标志设置、定时器时钟 Changing the Period Register TACCR0（改变的时期注册TACCR0）When changing TACCR0 while the timer is running, and counting in the down direction, the timercontinues its descent until it reaches zero. The value in TACCR0 is latched into TACL0 immediately however the new period takes effect after the counter counts down to zero当改变TACCR0定时器运行时，在上下方向计数，计时器继续下降，直到它达到零。被锁存到TACL0立即在TACCR0值，然而，新的时期后计数器计数的影响降为零When the timer is counting in the up direction, and the new period is greater than or equal to the oldperiod, or greater than the current count value, the timer counts up to the new period before countingdown. When the timer is counting in the up direction, and the new period is less than the current count value, the timer begins counting down. However, one additional count may occur before the counter begins counting down.当定时器计数方向向上，在新的时期，是大于或等于旧期间，或大于当前计数值，计数，计数前新时期下来。当定时器计数方向向上，在新的时期，是小于当前计数值，计时器开始倒计时。然而，一个额外的计数可能发生的柜台前开始倒计时。 Use of the Up/Down Mode（使用向上/向下模式）The up/down mode supports applications that require dead times between output signals (See sectionTimer_A Output Unit). For example, to avoid overload conditions, two outputs driving an H-bridge must never be in a high state simultaneously. In the example shown in Figure 12-9 the tdead is:向上/向下模式支持的应用程序需要输出信号之间的死区时间（见第定时器A输出单元） 。例如，为了避免过载条件下，两个输出驱动H桥必须永远不会同时在一个高的状态。在图12-9所示的例子中tdead是：tdead = ttimer (TACCR1 TACCR2)Where,tdead = Time during which both outputs need to be inactivettimer = Cycle time of the timer clockTACCRx = Content of capture/compare register xtdead = ttimer （ TACCR1 - TACCR2 ）在那里，tdead =时间在这两个输出需要是无效ttimer =定时器时钟周期时间TACCRx =内容捕获/比较寄存器xThe TACCRx registers are not buffered. They update immediately when written to. Therefore, any required dead time will not be maintained automaticallyTACCRx寄存器没有缓冲。他们立即更新时写入。因此，任何不会自动维护所需的死区时间Figure 12-9. Output Unit in Up/Down Mode（图12-9 。在向上/向下模式输出单元）12.2.4 Capture/Compare Blocks(12.2.4捕获/比较块)Two or three identical capture/compare blocks, TACCRx, are present in Timer_A. Any of the blocks may be used to capture the timer data, or to generate time intervals.两个或三个相同的捕捉/比较模块， TACCRx ，是目前在定时器A 。块中的任何可用于捕获定时器数据，或产生的时间间隔。Capture Mode（捕获模式）The capture mode is selected when CAP = 1. Capture mode is used to record time events. It can be used for speed computations or time measurements. The capture inputs CCIxA and CCIxB are connected toexternal pins or internal signals and are selected with the CCISx bits. The CMx bits select the captureedge of the input signal as rising, falling, or both. A capture occurs on the selected edge of the input signal. If a capture occurs:捕获模式选择第= 1时。捕捉模式是用来记录时间事件。它可以用来速度计算或测量时间。捕获输入CCIxA和CCIxB连接到外部引脚或内部信号和与CCISx位被选中。的的CMX位选择捕获上升，下降或输入信号的边缘。捕捉发生在输入选定的边缘信号。如果发生捕获： The timer value is copied into the TACCRx register The interrupt flag CCIFG is set定时器的值复制到TACCRx寄存器中断标志CCIFG的设置The input signal level can be read at any time via the CCI bit. MSP430x2xx family devices may have different signals connected to CCIxA and CCIxB. See the device-specific data sheet for the connections of these signals.输入信号电平可以在任何时间通过CCI位阅读。 MSP430x2xx系列设备可能有连接不同的信号到CCIxA和CCIxB 。看到连接设备特定数据表这些信号。The capture signal can be asynchronous to the timer clock and cause a race condition. Setting the SCS bit will synchronize the capture with the next timer clock. Setting the SCS bit to synchronize the capture signal with the timer clock is recommended. This is illustrated in Figure 12-10.捕捉信号可以是异步定时器时钟和造成的竞争条件。设置南海位将在下一个定时器时钟同步捕获。 SCS位设置同步捕获建议定时器的时钟信号。图12-10说明了这一点。 图12-10 。捕捉信号（南海= 1 ）Timer Clock？定时器时钟Overflow logic is provided in each capture/compare register to indicate if a second capture was performedbefore the value from the first capture was read. Bit COV is set when this occurs as shown in Figure 12-11. COV must be reset with software溢出逻辑在每个捕获/比较寄存器来表示，如果进行第二次捕捉之前，从第一次捕捉的值被读取。 COV的位被设置时，出现这种情况如图12-11 。 COV的必须重置软件 图12-11 。捕捉周期 Capture Initiated by Software（由软件引发的捕捉）Captures can be initiated by software. The CMx bits can be set for capture on both edges. Software then sets CCIS1 = 1 and toggles bit CCIS0 to switch the capture signal between VCC and GND, initiating a capture each time CCIS0 changes state:通过软件可以启动捕获。该的CMX位可以设置捕获的两边。然后软件设置CCIS1 = 1和切换位CCIS0 VCC和GND之间切换捕捉信号，启动一个捕捉每次CCIS0状态发生变化：MOV #CAP+SCS+CCIS1+CM_3,&TACCTLx ; Setup TACCTLxXOR #CCIS0,&TACCTLx ; TACCTLx = TAR Compare Mode（比较模式）The compare mode is selected when CAP = 0. The compare mode is used to generate PWM output signals or interrupts at specific time intervals. When TAR counts to the value in a TACCRx:比较模式选择第= 0时。被用来产生PWM输出比较模式在特定的时间间隔的信号或中断。当西藏自治区计数在TACCRx的价值： Interrupt flag CCIFG is set Internal signal EQUx = 1 EQUx affects the output according to the output mode The input signal CCI is latched into SCCI中断标志CCIFG的设置内部信号EQUx = 1 EQUx影响输出根据输出模式输入信号CCI的被锁存到SCCI12.2.5 Output Unit（12.2.5输出单位）Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on theEQU0 and EQUx signals.每个捕捉/比较块包含一个输出单元。输出单元是用来产生输出信号如PWM信号。每个输出单元的基础上，有八个经营模式产生的信号EQU0和EQUx信号 Output Modes（输出模式）The output modes are defined by the OUTMODx bits and are described in Table 12-2. The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0. Output modes 2, 3, 6, and 7 are not useful for output unit 0, because EQUx = EQU0. 定义由OUTMODx位输出模式，并在表12-2中所述。 OUTx信号改变模式0以外的所有模式的定时器时钟的上升沿。输出模式2，3 ， 6和7是没有用的输出单位为0 ， ，因为EQUx = EQU0 。 定时器A操作000输出输出信号OUTx的定义由OUTx位。在OUTx信号时立即更新OUTx更新。001设置输出设置时，定时器计数的TACCRx值。它保留设置，直到定时器复位，或直到另一个输出模式选择，并影响产量。010切换/复位计数的TACCRx值时，输出翻转。它被复位时，定时器计数的TACCR0价值011设置/重置输出设置时，定时器计数的TACCRx值。它被复位时，定时器计数的TACCR0价值100切换输出切换时计数的TACCRx值的。输出周期是双定时器周期101复位输出，复位时的定时器计数的TACCRx值的。保持复位状态，直到另一个输出模式选择，并影响产量。110切换/设置输出切换时，定时器计数的TACCRx值。它被设置时，定时器计数的TACCR0值111复位/输出设置被重置时，定时器计数的TACCRx值。它被设置时，定时器计数的TACCR0值 Output Example Timer in Up ModeThe OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from TACCR0 to zero, depending on the output mode. An example is shown in Figure 12-12 using TACCR0 and TACCR输出范例 - 向上模式定时器当定时器计数的TACCRx值，和从TACCR0到卷筒的OUTx信号改变零，取决于输出模式。显示了一个例子在图12-12使用TACCR0和TACCR1的 图12-13 。在连续模式下的定时器输出范例 Output Example Timer in Up/Down ModeThe OUTx signal changes when the timer equals TACCRx in either count direction and when the timerequals TACCR0, depending on the output mode. An example is shown in Figure 12-14 using TACCR0and TACCR输出范例 - 定时器向上/向下模式OUTx信号变化时，计时器等于TACCRx要么计数方向时，计时器等于TACCR0 ，根据输出模式。如图12-14所示的一个例子是使用TACCR0和TACCR2 图12-14 。输出范例定时器向上/向下模式NOTE: Switching Between Output Modes(注：输出模式之间的切换)When switching between output modes, one of the OUTMODx bits should remain set duringthe transition, unless switching to mode 0. Otherwise, output glitching can occur because aNOR gate decodes output mode 0. A safe method for switching between output modes i