EDA数字钟.doc

调时：shi加1，fen加1，miao清0；报时：59分50、52、54、56、58秒500HZ,0分0秒1000HZ;(一百八十多个警告) 分频器1HZ：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fpq1 isport(clk_in:in std_logic; clk_out:out std_logic);end ;architecture one of fpq1 is begin process(clk_in) constant counter_len:integer:=19999999; variable cnt:integer range 0 to counter_len; begin if clk_inevent and clk_in=1 then if cnt=counter_len then cnt:=0; else cnt:=cnt+1; end if; case cnt is when 0 to counter_len/2=clk_outclk_outclk_outclk_outclk_outclk_out=1; end case; end if; end process; end one;位选：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity wei isport ( clk1000 : in std_logic; q : buffer std_logic_vector(2 downto 0 );end;architecture one of wei issignal q1: std_logic_vector(2 downto 0 );beginprocess( clk1000 )beginif rising_edge(clk1000) thenif q1=111 then q1=000;else q1=q1+1;end if;end if;q duan1 duan1 duan1 duan1 duan1 duan1 duan1 duan1 duan1 duan1 duan1 duan2 duan2 duan2 duan2 duan2 duan2 duan2 duan2 duan2 duan2 duan2=null;end case;duan3 duan4 duan4 duan4 duan4 duan4 duan4 duan4 duan4 duan4 duan4 duan4 duan5 duan5 duan5 duan5 duan5 duan5 duan5 duan5 duan5 duan5 duan5=null;end case;duan6 duan7 duan7 duan7 duan7 duan7 duan7 duan7 duan7 duan7 duan7 duan7 duan8 duan8 duan8 duan8 duan8 duan8 duan8 duan8 duan8 duan8 duan8duanduanduanduanduanduanduanduanduan=null;end case;if shi=1 and clk1000=1 then s:=s+1;end if;if fen=1 and clk1000=1 then f:=f+1;end if;if miao=1 and clk1000=1 then m:=0; end if;if f=59 and (m=50 or m=52 or m=54 or m=56 or m=58) then rang=clk500;end if;if f=0 and m=0 then rangclk,clk_out=y1); u2:fpq500 port map(clk_in=clk,clk_out=y500); u3:fpq1000 port map(clk_in=clk,clk_out=y1000); u4:duan port map(clk1=y1,clk500=y500,clk1000=y1000