乘法器电路的设计

9.2乘法器设计,应用数字信号处理和数字通信地位影响系统的运行速度实现并行乘法器移位相加乘法器查找表乘法器加法树乘法器,9.2.1并行乘法器,结构用乘法运算符描述由EDA软件综合优点运算速度快缺点耗用资源多,【例9.4】8位并行乘法器modulemult(outcome,a,b);parametersize=8;inputsize:1a,b;/源操作数output2*size:1outcome;/乘积assignoutcome=a*b;/相乘endmodule,8位并行乘法器RTL图,9.2.2移位相加乘法器,结构移位寄存器加法器优点耗用资源少,【例9.16】8位二进制数的乘法modulemult_for(outcome,a,b);parametersize=8;inputsize:1a,b;output2*size:1outcome;reg2*size:1outcome;integeri;,always(aorb)beginoutcome=4h0;for(i=1;i=size;i=i+1)if(bi)outcome=outcome+(a(i-1);endendmodule,乘法器的功能仿真波形图,9.2.3查找表乘法器,结构操作数：地址乘积：存储器优点运算速度快缺点耗用存储资源多,设计思路,4位查找表乘法器Y=ABA=A122+A2B=B122+B2则Y=(A122+A2)(B122+B2)=A1B124+A1B222+A2B122+A2B2,8位查找表乘法器Y=ABA=A124+A2B=B124+B2则Y=(A124+A2)(B124+B2)=A1B128+A1B224+A2B124+A2B2,【例9.5】88查找表乘法器/*22查找表乘法器*/modulelookup(out,a,b,clk);output3:0out;/乘积input1:0a,b;/操作数inputclk;reg3:0out;reg3:0address;/存储器地址,always(posedgeclk)beginaddress=a,b;case(address)4h0:out=4b0000;4h1:out=4b0000;4h2:out=4b0000;4h3:out=4b0000;4h4:out=4b0000;4h5:out=4b0001;4h6:out=4b0010;4h7:out=4b009;,4h8:out=4b0000;4h9:out=4b0010;4ha:out=4b0100;4hb:out=4b090;4hc:out=4b0000;4hd:out=4b009;4he:out=4b090;4hf:out=4b1001;default:out=4bx;endcaseendendmodule,/*44查找表乘法器*/modulemult4x4(out,a,b,clk);output7:0out;/乘积input3:0a,b;/操作数inputclk;reg7:0out;reg1:0firsta,firstb;/操作数高2位reg1:0seconda,secondb;/操作数低2位wire3:0outa,outb,outc,outd;/乘积每2位1组,always(posedgeclk)beginfirsta=a3:2;seconda=a1:0;firstb=b3:2;secondb=b1:0;end,lookupm1(outa,firsta,firstb,clk),/元件调用m2(outb,firsta,secondb,clk),m3(outc,seconda,firstb,clk),m4(outd,seconda,secondb,clk);always(posedgeclk)beginout=(outa4)+(outb2)/乘积+(outc2)+outd;endendmodule,4位查找表乘法器仿真波形图,/*88查找表乘法器*/modulemult8x8(out,a,b,clk);output15:0out;/乘积input7:0a,b;/操作数inputclk;reg15:0out;reg3:0firsta,firstb;/操作数高4位reg3:0seconda,secondb;/操作数低4位wire7:0outa,outb,outc,outd;/乘积每8位1组,always(posedgeclk)beginfirsta=a7:4;seconda=a3:0;firstb=b7:4;secondb=b3:0;end,mult4x4n1(outa,firsta,firstb,clk),/元件调用n2(outb,firsta,secondb,clk),n3(outc,seconda,firstb,clk),n4(outd,seconda,secondb,clk);always(posedgeclk)beginout=(outa8)+(outb4)/乘积+(outc4)+outd;endendmodule,8位查找表乘法器仿真波形图,9.2.4加法树乘法器,结构底层：乘法器高层：多级加法器优点1个时钟周期完成,加法树乘法器结构框图,【例9.6】8位加法树乘法器moduleadd_tree(out,a,b,clk);output15:0out;/乘积input7:0a,b;/操作数inputclk;wire15:0out;wire15:0out1,c1;/加法器和wire13:0out2;wire11:0out3,c2;wire9:0out4;,reg14:0temp0;/最高位乘积reg13:0temp1;reg12:0temp2;reg11:0temp3;reg10:0temp4;reg9:0temp5;reg8:0temp6;reg7:0temp7;/最低位乘积,/*81乘法器*/function7:0mult8x1;input7:0operand;inputsel;beginmult8x1=(sel)?(operand):8b00000000;endendfunction,/*操作数b各位与操作数a相乘*/always(posedgeclk)begintemp7=mult8x1(a,b0);temp6=(mult8x1(a,b1)1;temp5=(mult8x1(a,b2)2;temp4=(mult8x1(a,b3)3;temp3=(mult8x1(a,b4)4;temp2=(mult8x1(a,b5)5;temp1=(mult8x1(a,b6)6;temp0=(mult8x1(a,b7)7;end,/*加法器树运算*/assignout1=temp0+temp1;assignout2=temp2+temp3;assignout3=temp4+temp5;assignout4=temp6+temp7;assignc1=out1+out2;assignc2=out3+out4;assignout=c1+c2;endmodule,8位加法树乘法器仿真波形图,四种乘法器的比较,9.3乘累加器（MAC）的设计,【例9.30】乘累加器（MAC）moduleMAC(out,opa,opb,clk,clr);output15:0out;input7:0opa,opb;inputclk,clr;wire15:0sum;reg15:0out;,function15:0mult;input7:0opa,opb;reg15:0result;integeri;beginresult=opa0?opb:0;for(i=1;i=7;i=i+1)begi