单片机相关资料74系列芯片总汇74hc221a

1、C1995 National Semiconductor Corporation TL/F/5325RRD-B30M105/Printed in U. S. A.MM54HC221A/MM74HC221A Dual Non-Retriggerable Monostable MultivibratorJanuary 1988MM54HC221A/MM74HC221ADual Non-Retriggerable Monostable MultivibratorGeneral DescriptionThe MM54/74HC221A high speed monostable multivibra-

2、 is econds, R is in ohms, and C is in farads. All inputs are tors (one shots) utilize advanced silicon-gate CMOS tech- protected from damage due to static discharge by diodes to nology. They feature speeds comparable to low power VCC and ground.Schottky TTL circuitry while retaining the low power an

3、dhigh noise immunity characteristic of CMOS circuits.FeaturesEach multivibrator features both a negative, A, and a posi-Y Typical propagation delay: 40 ns tive, B, transition triggered input, either of which can beY Wide power supply range: 2V 6Vused as an inhibit input. Also included is a clear inp

4、ut thatY Low quiescent current: 80 mA maximum (74HCSeries)when taken low resets the one shot. The HC221A can beY Low input current: 1 mA maximum triggered on the positive transition of the clear while A isY Fanout of 10 LS-TTL loadsheld low and B is held high.Y Simple pulse width formula T e RCThe H

5、C221A is a non-retriggerable, and therefore cannotY Wide pulse range: 400 ns to % (typ)be retriggered until the output pulse times out.Y Part to part variation: g5% (typ)Pulse width stability over a wide range of temperature andY Schmitt Trigger A & B inputs enable infinite signal inputsupply is ach

6、ieved using linear CMOS techniques. The out-put pulse equation is simply: PWe(REXT) (CEXT); where PW rise or fall timesConnection DiagramDual-In-Line PackageTiming ComponentNote: Pin 6 and Pin 14 must be hard- wired to GND.TL/F/5325 2TL/F/5325 1Top ViewOrder Number MM54HC221A or MM74HC221ATruth Tabl

7、eH e High Level L e Low Levelue Transition from Low to Highve Transition from High to Low?e One High Level Pulse?e One Low Level Pulse X e IrrelevantInputsOutputsClearABQQL X X H HuX H X LvLX X LuH HL L L?H H H?2Absolute Maximum Ratings (Notes1& 2)Operating ConditionsIf Military/Aerospace specified

8、devices are required,MinMaxUnits please contact the National Semiconductor SalesSupply Voltage (VCC)26V Office/Distributors for availability and specifications.DC Input or Output Voltage0VCCV Supply Voltage (VCC)b0.5V to a7.0V(VIN, VOUT)DC Input Voltage (VIN)b1.5V to VCCa1.5VOperating Temp. Range (T

9、A)DC Output Voltage (VOUT)b0.5V to VCCa0.5VMM74HCb40 a85?C Clamp Diode Current (IIK, IOK)g20 mAMM54HCb55 a125 ?C DC Output Current, per pin (IOUT)g25 mAMaximum Input Rise and FallTime (Clear Input)DC VCC or GND Current, per pin (ICC)g50 mAVCCe2.0V1000nsStorage Temperature Range (TSTG) b65?C to a150?

10、CVCCe4.5V500ns Power Dissipation (PD)VCCe6.0V400ns(Note 3)600 mWS.O. Package only500 mWLead Temperature(TL) (Soldering 10 seconds)260?CDC Electrical Characteristics (Note 4)Note 2: Unless otherwise specified all voltages are referenced to ground.Note 3: Power Dissipation temperature derating ? plast

11、ic N package: b12 mW/?C from 65?C to 85?C; ceramic J package: b12 mW/?C from 100?C to 125?C.Note 4: For a power supply of 5V g10% the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst-case VIH and VIL occur at V

12、CCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.SymbolParameterConditionsVCCTAe25?C74HCTAeb40 to 85?C54HCTAeb55 to 125?CUnitsTypGuaranteed LimitsVIHMinimum H

13、igh Level Input Voltage2.0V4.5V6.0V1.53.154.21.53.154.21.53.154.2V V VVILMaximum Low Level Input Voltage2.0V4.5V6.0V0.30.91.20.30.91.20.30.91.2V V VVOHMinimum High Level Output VoltageVINeVIH or VILlIOUTls20 mA2.0V4.5V6.0V2.04.56.01.94.45.91.94.45.91.94.45.9V V VVINeVIH or VILlIOUTls4.0 mAlIOUTls5.2

14、 mA4.5V6.0V4.25.73.985.483.845.343.75.2V VVOLMaximum Low Level Output VoltageVINeVIH or VILlIOUTls20 mA2.0V4.5V6.0V0000.10.10.10.10.10.10.10.10.1V V VVINeVIH or VILlIOUTls4.0 mAlIOUTls5.2 mA4.5V6.0V0.20.20.260.260.330.330.40.4V VIINMaximum Input Current (P7, 15)VINeVCC or GND6.0Vg0.5g5.0g5.0mAIINMax

15、imum Input Current (all other p )VINeVCC or GND6.0Vg0.1g1.0g1.0mAICCMaximum Quiescent Supply Current (standby)VINeVCC or GND IOUTe0 mA6.0V8.080160mAICCNote 1: MaMaximum Active Supply Current (per monostable)ximum Ratings are those values beyonVINeVCC or GND R/CEXT e 0.5VCCd which damage to the d2.0V

16、4.5V6.0Vevice ma360.330.7y occur.801.02.01101.32.61301.63.2mA mA mA3AC Electrical Characteristics VCCe5V, TAe25?C, CLe15 pF, tretfe6 nsAC Electrical Characteristics CLe50 pF, tretfe6 ns(unless otherwise specified)SymbolParameterConditionsVCCTAe25?C74HCTAeb40 to 85?C54HCTAeb55 to 125?CUnitsTypGuarant

17、eed LimitstPLHMaximum Trigger Propagation Delay A, B or Clear to Q2.0V4.5V6.0V772621169423219451392105744ns ns nstPHLMaximum Trigger Propagation Delay A, B or Clear to Q2.0V4.5V6.0V882924197483822960462506751ns ns nstPHLMaximum Propagation Delay Clear to Q2.0V4.5V6.0V542319114342813241331434536ns ns

18、 nstPLHMaximum Propagation Delay Clear to Q2.0V4.5V6.0V562520116362913542341474637ns ns nstWMinimum Pulse Width A, B, Clear2.0V4.5V6.0V571712123302114437271574230ns ns nstREMMinimum Clear Removal Time2.0V4.5V6.0V000000000ns ns nstTLH, tTHLMaximum Output Rise and Fall Time2.0V4.5V6.0V3087751513951916

19、1102219ns ns nstWQ(MIN)Minimum Output Pulse WidthCEXTe28 pF REXTe2 kXREXTe6 kX (VCCe2V)2.0V4.5V6.0V1.5450380ms ns nstWQOutput Pulse WidthCEXTe0.1 mF REXTe10 kXMin5.0V10.90.860.85msMax5.0V11.11.141.15msCPDPower Dissipation Capacitance (Note 5)87pFCINMaximum Input Capacitance (P 7& 15)12202020pFCINMax

20、imum Input Capacitance (other inputs)6101010pFNote 5: CPD determines the no load dynamic power consumption, PDeCPD VCC 2 aICC VCC, and the no load dynamic current consumption, IS eCPD VCCf aICC.fSymbolParameterConditionsTypGuaranteed LimitUnitstPLHMaximum Trigger Propagation Delay A, B or Clear to Q

21、2236nstPHLMaximum Trigger Propagation Delay A, B or Clear to Q2542nstPHLMaximum Propagation Delay Clear to Q2031nstPLHMaximum Propagation Delay Clear to Q2233nstWMinimum Pulse Width A, B or Clear1426nstREMMinimum Clear Removal Time0nstWQ(MIN)Minimum Output Pulse WidthCEXTe28 pF REXTe2 kX400nstWQOutp

22、ut Pulse WidthCEXTe1000 pF REXTe10 kX10ms4Logic DiagramTL/F/5325 5Theory of OperationTL/F/5325 6j POSITIVE EDGE TRIGGER m NO RETRIGGERINGk NEGATIVE EDGE TRIGGER n RESET PULSE SHORTENINGl POSITIVE EDGE TRIGGER o CLEAR TRIGGERFIGURE 15TRIGGER OPERATIONAs shown in Figure 1 and the logic diagram before

23、an input It should be noted that in the quiescent state CEXT is fully trigger occurs, the monostable is in the quiescent state with charged to VCC causing the current through resistor REXT to the Q output low, and the timing capacitor CEXT completely be zero. Both comparators are off with the total

24、device charged to VCC. When the trigger input A goes from VCC to current due only to reverse junction leakages. An added GND (while inputs B and clear are held to VCC) a valid trig- feature of the HC221 is that the output latch is set via the ger is recognized, which turns on comparator C1 and N- in

25、put trigger without regard to the capacitor voltage. Thus, channel transistor N1 j. At the same time the output latch propagation delay from trigger to Q is independent of the is set. With transistor N1 on, the capacitor CEXT rapidly dis- value of CEXT, REXT, or the duty cycle of the input wave- cha

26、rges toward GND until VREF1 is reached. At this point form.the output of comparator C1 changes state and transistor The HC221 is non-retriggerable and will ignore input tran-N1 turns off. Comparator C1 then turns off while at the same sitions on A and B until it has timed out l and m. time comparato

27、r C2 turns on. With transistor N1 off, the ca-pacitor CEXT beg to charge through the timing resistor, RESET OPERATIONREXT, toward VCC. When the voltage across CEXT equals These one shots may be reset during the generation of the VREF2, comparator C2 changes state causing the output output pulse. In

28、the reset mode of operation, an input pulse latch to reset (Q goes low) while at the same time disabling on clear sets the reset latch and causes the capacitor to be comparator C2. This ends the timing cycle with the monosta- fast charged to VCC by turning on transistor Q1 n. When ble in the quiesce

29、nt state, waiting for the next trigger.the voltage on the capacitor reaches VREF2, the reset latch A valid trigger is also recognized when trigger input B goes will clear and then be ready to accept another pulse. If the from GND to VCC (while input A is at GND and input clear is clear input is held

30、 low, any trigger inputs that occur will be at VCCk ). The HC221 can also be triggered when clear inhibited and the Q and Q outputs of the output latch will goes from GND to VCC (while A is at Gnd and B is at not change. Since the Q output is reset when an input low VCCo ).level is detected on the C

31、lear input, the output pulse T canbe made significantly shorter than the minimum pulse widthspecification.Typical OutputPulse WidthTypical Distribution of OutputTypical 1ms Pulse Width vs. Timing ComponentsPulse Width, Part to PartVariation vs. SupplyTL/F/5325 8TL/F/5325 9TL/F/5325 7Minimum REXT vs.

32、Typical 1 ms Pulse WidthSupply VoltageVariation vs. TemperatureTL/F/5325 10TL/F/5325 11Note: R and C are not subjected to temperature. The C is polypropylene.National doesnotassumeanyresponsibility for useofanycircuitrydescribed, nocircuitpatentlicenses areimplied and National reservestherightatanyt

33、imewithoutnotice tochangesaidcircuitryandspecifications.MM54HC221A/MM74HC221A Dual Non-Retriggerable Monostable MultivibratorPhysical Dimensions inches (millimeters)Ceramic Dual-In-Line Package (J)Order Number MM54HC221AJ or MM74HC221AJ NS Package Number J16AMolded Dual-In-Line Package (N) Order Number MM74HC221AJN NS Package Number N16ELIFE SUPPORT POLICYNATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: