可变模计数器

1、一、实验目的:1. 掌握用 VHDL 硬件描述语言做电路综合设计方法。2. 熟悉掌握程序的编译、仿真、生成模块及芯片引脚号码锁定方法并下载到目标芯片。 二、实验仪器:ZY11EDA13BE 型实验箱三、实验内容及要求:1. 设计一个可变模计数器。2. 设计一个可变模计数器, 计数器有 3个触发器构成, 在外部控制信号 S2和 S1的控制 下分别实现模 3、模 5、模 7和模 8计数器,即(1 S2S1=00时,实现模 3计数,触发器的状态一次 0 1 2 0;(2 S2S1=01时,实现模 5计数,触发器的状态一次 0 1 2 3 4 0;(3 S2S1=10时,实现模 7计数,触发器的状态一

2、次 0 1 2 3 4 5 6 0;(4 S2S1=11时,实现模 7计数,触发器的状态一次 0 1 2 3 4 5 6 7 0; 并将结果输出到数码管上。四实验程序二四译码部分LIBRARY IEEE;ENTITY M2_45 ISPORT(A: IN STD_LOGIC_VECTOR(1 DOWNTO 0;Y3,Y2,Y1,Y0: BUFFER STD_LOGIC;END M2_45;ARCHITECTURE A OF M2_45 ISSIGNAL SEL :STD_LOGIC_VECTOR(1 DOWNTO 0;SIGNAL QN :STD_LOGIC_VECTOR(2 DOWNTO 0

3、;BEGINSEL(0<=A(0;SEL(1<=A(1;WITH SEL SELECTQN<="0001"WHEN"00","0010"WHEN"01","0100"WHEN"10","1000"WHEN"11","0000"WHEN OTHERS;Y0<=QN(0;Y1<=QN(1;Y2<=QN(2;Y3<=QN(3;END A;模三部分LIBRARY IEEE;ENTIT

4、Y MO3 ISPORT(CP,EN:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(2 DOWNTO 0 ;END MO3;ARCHITECTURE A OF MO3 ISSIGNAL QN:STD_LOGIC_VECTOR(2 DOWNTO 0 ; BEGINPROCESS(CP,ENBEGINIF(EN='0'THENQN<="000"ELSIF(CP'EVENT AND CP='1'THENIF(QN="010"THENQN<="000"ELSEQN&

5、lt;=QN+1;END IF;END IF;END PROCESS;Q<=QN;END A;模五部分LIBRARY IEEE;ENTITY MO5 ISPORT(CP,EN:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(2 DOWNTO 0 ;END MO5;ARCHITECTURE A OF MO5 ISSIGNAL QN:STD_LOGIC_VECTOR(2 DOWNTO 0 ; BEGINPROCESS(CP,ENBEGINIF(EN='0'THENQN<="000"ELSIF(CP'EVENT AND

6、CP='1'THENIF(QN="100"THENQN<="000"ELSEQN<=QN+1;END IF;END IF;END PROCESS;Q<=QN;END A;模七部分LIBRARY IEEE;ENTITY MO7 ISPORT(CP,EN:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(2 DOWNTO 0 ;END MO7;ARCHITECTURE A OF MO7 ISSIGNAL QN:STD_LOGIC_VECTOR(2 DOWNTO 0 ; BEGINPROCESS(CP,E

7、NBEGINIF(EN='0'THENQN<="000"ELSIF(CP'EVENT AND CP='1'THENIF(QN="110"THENQN<="000"ELSEQN<=QN+1;END IF;END IF;END PROCESS;Q<=QN;END A;模八部分LIBRARY IEEE;ENTITY MO8 ISPORT(CP,EN:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(2 DOWNTO 0;END MO8;ARCHITECTU

8、RE A OF MO8 ISSIGNAL QN:STD_LOGIC_VECTOR(2 DOWNTO 0 ;BEGINPROCESS(CP,ENBEGINIF(EN='0'THENQN<="000"ELSIF(CP'EVENT AND CP='1'THENIF(QN="111"THENQN<="000"ELSEQN<=QN+1;END IF;END IF;END PROCESS;Q<=QN;END A;动态扫描部分LIBRARY IEEE;ENTITY CTL ISPORT

9、(CP:IN STD_LOGIC;MO3,MO5,MO7,MO8:IN STD_LOGIC_VECTOR(2 DOWNTO 0; SEL:IN STD_LOGIC_VECTOR(1 DOWNTO 0;COUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0;END CTL;ARCHITECTURE A OF CTL ISBEGINPROCESS(CPBEGINIF(CP'EVENT AND CP='1'THENCASE SEL ISWHEN "00"=>COUT<=MO3(2 DOWNTO 0;WHEN "01&

10、quot;=>COUT<=MO5(2 DOWNTO 0;WHEN "10"=>COUT<=MO7(2 DOWNTO 0;WHEN "11"=>COUT<=MO8(2 DOWNTO 0;WHEN OTHERS=>COUT<="000"END CASE;END IF;END PROCESS;END A;BCD 译码部分LIBRARY IEEE;ENTITY BCDYM ISPORT(D:IN STD_LOGIC_VECTOR(2 DOWNTO 0; Q:OUT STD_LOGIC_VECTO

11、R(6 DOWNTO 0; END BCDYM;ARCHITECTURE QQ OF BCDYM ISBEGINPROCESS(DBEGINCASE D ISWHEN"000"=>Q<="0111111"WHEN"001"=>Q<="0000110"WHEN"010"=>Q<="1011011"WHEN"011"=>Q<="1001111"WHEN"100"=>Q<="1100110"WHEN"101"=>Q<="1101101"WHEN"110"=>Q<="1111101"WHEN"111"=>Q<="0000111"WHEN OTHERS=>Q<="0000000"END CASE;END PROCESS;END QQ;五实验电路图 MO3 CP INPUT VCC CP Q2.0 EN 0. inst3 M2_45 A1.0