128入128出的tst接线器

1、通信集成电路实验报告128 入 128出的 tst 接线器128入 128出的 tst 接线器T-S-T交换网络是由输入级 T接线器（TA ）和输出级T接线器（TB ）,中间接有S型时分接 线器组成，T 模块包括 16 个 T8 接线器， T 输入同样调用了 16 次，在 S 接线器在总的模块调用，实现 了数据信息的传输。S 接线器将数据放入 16 个寄存器中，通过输出得到控制。 程序module c_b(clk,rst,data_in,data_out);input clk,rst;input data_in;output 7:0 data_out;reg 2:0 num;reg 7:0 d

2、ata_out;always (posedge clk)if (rst)begindata_out=8b0000_0000; num=3b000;endelsebegindata_out=data_out6:0,data_in;num=num+1;endendmodulemodule mux(out,hw0,hw1,hw2,hw3,hw4,hw5,hw6,hw7,sel); output 7:0 out;input 7:0 hw0,hw1,hw2,hw3,hw4,hw5,hw6,hw7;input 2:0 sel;reg 7:0 out;always (hw0 or hw1 or hw2 or

3、 hw3 or hw4 or hw5 or hw6 or hw7 or sel) begincase(sel)3b000: out=hw0;3b001: out=hw1;3b010: out=hw2;3b011: out=hw3;3b100: out=hw4;3b101: out=hw5;3b110: out=hw6;3b111: out=hw7;endcaseendendmodulemodule s_ram ( wr_clk,wr_en,wr_addr,data_in,rd_clk,rd_en,rd_addr,data_out );input wr_clk,wr_en,rd_clk,rd_e

4、n;input 7:0 data_in;input 7:0 wr_addr,rd_addr;output 7:0 data_out;reg 7:0 data_out;reg 7:0 mem 255:0;always (posedge wr_clk)if(wr_en)memwr_addr = data_in;always (posedge rd_clk)if(rd_en)data_out = memrd_addr;endmodule module c_ram ( wr_clk,wr_en,wr_addr,data_in,rd_clk,rd_en,rd_addr,data_out ); input

5、 wr_clk,wr_en,rd_clk,rd_en;input 7:0 data_in;input 7:0 wr_addr,rd_addr;output 7:0 data_out;reg 7:0 data_out;reg 7:0 mem 255:0;always (posedge wr_clk)if(wr_en)memwr_addr = data_in;always (posedge rd_clk)if(rd_en)data_out = memrd_addr;endmodulemodule fenlu(data_in,sel,reg0,reg1,reg2,reg3,reg4,reg5,reg

6、6,reg7);input 7:0 data_in;input 2:0 sel;output 7:0reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7;reg 7:0reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7;always (data_in)case (sel)3b000: reg0=data_in;3b001: reg1=data_in;3b010: reg2=data_in;3b011: reg3=data_in;3b100: reg4=data_in;3b101: reg5=data_in;3b110: reg6=data_

7、in;3b111: reg7=data_in; endcaseendmodulemodule yiwei(clk,rst,data_in,data_out); input clk,rst;input 7:0data_in;output data_out;reg data;always (posedge clk)if(rst)data=0;elsedata=data_in7;assign data_in=data_in6:0,1b0;assign data_out=data;endmodulemodule bit(clk,rst,count_8,count_256);input rst,clk;

8、output 2:0 count_8;output 7:0 count_256;reg 2:0 count_8;reg 7:0 count_256;always (posedge clk ) begin if(rst) begincount_8 = 3b000; count_256=8b0000_0000; end begincount_256 = count_256+1; if(count_256%8=0) count_8 = count_8 +1; endelseendendmodulemodulemux_s( hw0,hw1,hw2,hw3,hw4,hw5,hw6,hw7,hw8,hw9

9、,hw10,hw11,hw12,hw13,hw14,hw15,out0,out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15, sel0,sel1, sel2, sel3, sel4, sel5, sel7,sel8,sel9,sel10,sel11,sel12,sel13,sel14,sel15);outputout0,out1,out2,out3,out4,out5,out6,out7 ,out8,out9,out10,out11,out12,out13,out14,out15;se

10、l6,7:0out1=hw6;out1=hw7;out1=hw8;out1=hw9;out1=hw10;out1=hw11;out =hw12;4b1101out1=hw13;out0=hw0;4b00014b00104b00114b01004b01014b01104b0111out0=hw1;out0=hw2;out0=hw3;out0=hw4;out0=hw5;out0=hw6;out0=hw7;4b10004b10014b1010out0=hw8;out0=hw9; out0=hw10;end4b10114b11004b11014b11104b1111endcaseout0=hw11;o

11、ut0=hw12;out0=hw13;out0=hw14;out0=hw15;always (hw0 or hw1 or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10 or hw11 or hw12 or hw13 or hw14 or hw15or sel1)begincase(sel0)4b00004b00014b00104b0011out1=hw0; out1=hw1; out1=hw2; out1=hw3;4b01004b0101out1=hw4;out1=hw5;7:0inputhw0,hw1,hw2,hw3

12、,hw4,hw5,hw6,hw7 ,hw8,hw9,hw10,hw11,hw12,hw13,hw14,hw15; input 3:0 sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7 ,sel8,sel9,sel10,sel11,sel12,sel13,sel14,sel15; reg 7:0 out0,out1,out2,out3,out4,out5,out6,out7 ,out8,out9,out10,out11,out12,out13,out14,out15; always (hw0 or hw1 or hw2 or hw3 or hw4 or

13、 hw5 or hw6 or hw7 or hw8 or hw9 or hw10 or hw11 or hw12 or hw13 or hw14 or hw15 or sel0)begin case(sel0) 4b00004b0110 4b0111 4b1000 4b1001 4b1010 4b1011 4b11004b0010: out5=hw2;4b0011: out5=hw3;4b0100: out5=hw4;4b0101: out5=hw5;4b0110: out5=hw6;4b0111: out5=hw7;4b1000: out5=hw8;4b1001: out5=hw9;out3

14、=hw4;out3=hw5;out3=hw6;out3=hw7;out3=hw8;out3=hw9;out3=hw10;4b1011out3=hw11;4b1110: out1=hw14;4b1111: out1=hw15;endcaseendalways (hw0 or hw1 or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or hw13 or hw14 or hw15 or sel2) begincase(sel0)4b00004b00014b00104b00114b01004b

15、01014b0110out2=hw0; out2=hw1; out2=hw2; out2=hw3; out2=hw4; out2=hw5; out2=hw6;4b01114b10004b1001out2=hw7;out2=hw8;out2=hw9;4b10104b10114b11004b11014b11104b1111out2=hw10;out2=hw11;out2=hw12;out2=hw13;out2=hw14;out2=hw15;out3=hw0;out3=hw1;4b00014b00104b0011out3=hw2;out3=hw3;endcase endalways (hw0 or

16、hw1 or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or hw13 or hw14 or hw15 or sel3) begincase(sel0) 4b00004b0100 4b0101 4b0110 4b0111 4b1000 4b1001 4b10104b1100: out3=hw12;4b1101: out3=hw13;4b1110: out3=hw14;4b1111: out3=hw15;endcaseendalways (hw0 or hw1 or hw2 or hw3

17、 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or hw13 or hw14 or hw15 or sel4)begin case(sel0)4b00004b00014b00104b00114b0100out4=hw0; out4=hw1; out4=hw2; out4=hw3; out4=hw4;4b01014b01104b0111out4=hw5;out4=hw6;out4=hw7;4b10004b10014b10104b10114b11004b11014b1110out4=hw8;out4=hw9; o

18、ut4=hw10; out4=hw11; out4=hw12; out4=hw13; out4=hw14;4b1111out4=hw15;endcaseendalways (hw0 or hw1 or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or hw13 or hw14 or hw15 or sel5) begincase(sel0)4b0000: out5=hw0;4b0001: out5=hw1; b1010: out5=hw10;4b1011: out5=hw11;4b110

19、0: out5=hw12;4b1101: out5=hw13;4b1110: out5=hw14; b0111: out7=hw7;4b1111: out5=hw15;endcaseendalways (hw0 or hw1 or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or hw13 or hw14 or hw15 or sel6) begincase(sel0)4b00004b00014b0010out6=hw0;out6=hw1;out6=hw2;4b00114b01004b0

20、101out6=hw3;out6=hw4;out6=hw5;4b01104b01114b10004b10014b10104b10114b1100out6=hw6;out6=hw7;out6=hw8;out6=hw9; out6=hw10; out6=hw11; out6=hw12;4b11014b11104b1111out6=hw13;out6=hw14;out6=hw15;endcase endalways (hw0 or hw1 or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or

21、 hw13 or hw14 or hw15 or sel7) begincase(sel0)4b0000: out7=hw0;4b0001: out7=hw1;4b0010: out7=hw2;4b0011: out7=hw3;4b0100: out7=hw4;4b0101: out7=hw5;4b0110: out7=hw6;4b1000: out7=hw8;4b1001: out7=hw9;4b1010: out7=hw10;4b1011: out7=hw11;4b1100: out7=hw12;4b0101: out9=hw ;4b1101: out7=hw13;4b1110: out7

22、=hw14;4b1111: out7=hw15;endcaseendalways (hw0 or hw1 or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or hw13 or hw14 or hw15 or sel8) begincase(sel0)4b0000out8=hw0;4b00014b00104b0011out8=hw1;out8=hw2;out8=hw3;4b01004b01014b01104b01114b10004b10014b1010out8=hw4;out8=hw5;

23、out8=hw6;out8=hw7;out8=hw8;out8=hw9; out8=hw10;4b10114b11004b1101out8=hw11;out8=hw12;out8=hw13;4b11104b1111out8=hw14;out8=hw15;endcase endalways (hw0 or hw1 or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or hw13 or hw14 or hw15 or sel9) begincase(sel0)4b0000: out9=hw0

24、;4b0001: out9=hw1;4b0010: out9=hw2;4b0011: out9=hw3;4b0100: out9=hw4;4b0001: out11=hw1;4b0011: out11=hw3;4b0110: out9hw6;4b0111: out9hw7;4b1000: out9hw8;4b1001: out9hw9;4b1010: out9hw10;4b1011: out9hw11;4b1100: out9hw12;4b1101: out94b1110: out9hw13;hw14;4b1111: out9hw15;endcaseendalways (hw0 or hw1

25、or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or hw13 or hw14 or hw15 or sel10) begincase(sel0)4b00004b0001out10=hw0;out10=hw1;4b0010out10=hw2;4b0011out10=hw3;4b0100out10=hw4;4b0101out10=hw5;4b0110out10=hw6;4b0111out10=hw7;4b1000out10=hw8;4b1001out10=hw9;4b10104b1011

26、out10=hw10;out10=hw11;4b1100out10=hw12;4b1101out10=hw13;4b1110out10=hw14;4b1111out10=hw15;endcase endalways (hw0 or hw1 or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or hw13 or hw14 or hw15 or sel11) begincase(sel0)4b0000: out11=hw0;4b0010: out11=hw2;out11=hw4;out11=

27、hw5;out11=hw6;out11=hw ;out11=hw8;4b0001: out13=hw1;4b01004b01014b01104b01114b10004b1001out11=hw9;4b10104b10114b1100out11=hw10;out11=hw11;out11=hw12;4b11014b11104b1111out11=hw13;out11=hw14;out11=hw15;endcaseendalways (hw0 or hw1 or hw2 or hw3 or hw4 or hw5 hw10or hw6 or hw7 or hw8 or hw9 oror hw11 o

28、r hw12 or hw13 or hw14 or hw15 or sel12) begincase(sel0)4b00004b00014b00104b00114b01004b01014b0110out12=hw0; out12=hw1; out12=hw2; out12=hw3; out12=hw4; out12=hw5; out12=hw6;4b01114b10004b1001out12=hw7;out12=hw8;out12=hw9;4b10104b10114b11004b11014b1110out12=hw10; out12=hw11; out12=hw12;out12=hw13;ou

29、t12=hw14;4b1111out12=hw15;endcase endalways (hw0 or hw1 or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or hw13 or hw14 or hw15 or sel13) begincase(sel0)4b0000: out13=hw0;out13=hw2;out13=hw3;out13=hw4;out13=hw5;out =hw6;end4b00104b00114b01004b01014b01104b01114b10004b10

30、014b10104b10114b11004b11014b11104b1111endcaseout13=hw7;out13=hw8;out13=hw9; out13=hw10;out13=hw11;out13=hw12;out13=hw13;out13=hw14;out13=hw15;always (hw0 or hw1 or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or hw13 or hw14 or hw15 or sel14) begincase(sel0) 4b00004b00

31、014b00104b0011out14=hw0;out14=hw1;out14=hw2;out14=hw3;4b01004b01014b0110out14=hw4;out14=hw5;out14=hw6;4b01114b10004b10014b10104b1011out14=hw7;out14=hw8;out14=hw9; out14=hw10; out14=hw11;4b11004b1101out14=hw12;out14=hw13;4b11104b1111out14=hw14;out14=hw15;endcase endalways (hw0 or hw1 or hw2 or hw3 or

32、 hw4 or hw5 or hw6 or hw7 or hw8 or hw9 or hw10or hw11 or hw12 or hw13 or hw14 or hw15 or sel15) beginout15=hw0;out15=hw1;out15=hw2;out15=hw3;out =hw4;case(sel0)4b00004b00014b00104b00114b01004b01014b01104b0111out15=hw5;out15=hw6;out15=hw7;4b10004b10014b10104b10114b11004b11014b1110out15=hw8;out15=hw9

33、; out15=hw10; out15=hw11; out15=hw12; out15=hw13; out15=hw14;4b1111out15=hw15;endcaseend endmodule module c_ram_s ( wr_clk,wr_en,wr_addr,data_in,rd_clk,rd_en,rd_addr,data_out ); input wr_clk,wr_en,rd_clk,rd_en;input 7:0 data_in;input 7:0 wr_addr,rd_addr;output 23:0 data_out;reg 7:0 data_out;reg 7:0

34、mem 255:0;always (posedge wr_clk)if(wr_en) memwr_addr = data_in;always (posedge rd_clk) if(rd_en)data_out = memrd_addr;endmodule module T8(data_in,clk,rst,wr,wr_addr,wr_en,rd_en,data,ts);input data_in;input 7:0wr_addr;input clk,rst,wr,wr_en,rd_en;input 7:0 data;output 7:0 ts;wire 7:0 data_out_0,data

35、_out_1,data_out_2,data_out_3,data_out_4,data_out_5, data_out_6,data_out_7;wire 7:0 count_256,data_out_c,data_out_cb;wire 2:0 count_8;wire 7:0 reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7;c_b c0(.clk(clk),.rst(rst),.data_in(data_in),.data_out(data_out_0);c_b c1(.clk(clk),.rst(rst),.data_in(data_in),.data_

36、out(data_out_1);c_b c2(.clk(clk),.rst(rst),.data_in(data_in),.data_out(data_out_2);c_b c3(.clk(clk),.rst(rst),.data_in(data_in),.data_out(data_out_3);c_b c4(.clk(clk),.rst(rst),.data_in(data_in),.data_out(data_out_4);c_b c5(.clk(clk),.rst(rst),.data_in(data_in),.data_out(data_out_5);c_b c6(.clk(clk)

37、,.rst(rst),.data_in(data_in),.data_out(data_out_6);c_b c7(.clk(clk),.rst(rst),.data_in(data_in),.data_out(data_out_7);muxmm(.out(data_out_cb),.hw0(data_out_0),.hw1(data_out_1),.hw2(data_out_2),.hw3(data_out_3), .hw4(data_out_4),.hw5(data_out_5),.hw6(data_out_6),.hw7(data_out_7),.sel(count_8);s_ram s

38、rom(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(data_out_cb), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out_c),.data_out(ts);c_ram crom(.wr_clk(clk),.wr_en(wr),.wr_addr(wr_addr),.data_in(data),.rd_clk(clk),.rd_en(rd_en),.rd_addr(count_256),.data_out(data_out_c);bit bi(.clk(clk),.rst(rst),

39、.count_8(count_8),.count_256(count_256);endmodulemodule t8_out(data_in,clk,rst,wr,wr_addr,wr_en,rd_en,hwo0,hwo1,hwo2,hwo3,hwo4,hwo5,hwo6,hwo7);input data_in;input 7:0wr_addr;input clk,rst,wr,wr_en,rd_en;output hwo0,hwo1,hwo2,hwo3,hwo4,hwo5,hwo6,hwo7;wire hwo0,hwo1,hwo2,hwo3,hwo4,hwo5,hwo6,hwo7;wire

40、7:0 count_256,data_out_c,data_out_cb,ts;wire 2:0 count_8;wire 7:0 reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7;s_ram srom(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(data_out_cb), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out_c),.data_out(ts);fenlu fl(.data_in(data_out_s),.sel(count_8),.reg0(r

41、eg0),.reg1(reg0),.reg2(reg2), .reg3(reg3),.reg4(reg4),.reg5(reg5),.reg6(reg6),.reg7(reg7);yiwei yw0(.clk(count_2562),.rst(rst),.data_in(reg0),.data_out(hwo0);yiwei yw1(.clk(count_2562),.rst(rst),.data_in(reg1),.data_out(hwo1);yiwei yw2(.clk(count_2562),.rst(rst),.data_in(reg2),.data_out(hwo2);yiwei

42、yw3(.clk(count_2562),.rst(rst),.data_in(reg3),.data_out(hwo3);yiwei yw4(.clk(count_2562),.rst(rst),.data_in(reg4),.data_out(hwo4);yiwei yw5(.clk(count_2562),.rst(rst),.data_in(reg5),.data_out(hwo5);yiwei yw6(.clk(count_2562),.rst(rst),.data_in(reg6),.data_out(hwo6);yiwei yw7(.clk(count_2562),.rst(rs

43、t),.data_in(reg7),.data_out(hwo7);bit bi(.clk(clk),.rst(rst),.count_8(count_8),.count_256(count_256);endmodule module tst(data_in,clk,rst,wr,wr_addr,wr_addr_s,wr_en,rd_en,data,hwo0,hwo1,hwo2,hwo3,hwo4,hwo5,hwo6,hwo7);input data_in;input 7:0wr_addr;input 23:0 wr_addr_s;input clk,rst,wr,wr_en,rd_en;in

44、put 7:0 data;output hwo0,hwo1,hwo2,hwo3,hwo4,hwo5,hwo6,hwo7;7:07:0wirehw0,hw1,hw2,hw3,hw4,hw5,hw6,hw7,hw8,hw9,hw10,hw11,hw12,hw13,hw14,hw15;wire 7:0 count_256,data_out;wire 2:0 count_8;wire 7:0 ou0,ou1,ou2,ou3,ou4,ou5,ou6,ou7,ou8,ou9,ou10,ou11,ou12,ou13,ou14,ou15;wireout0,out1,out2,out3,out4,out5,ou

45、t6,out7,out8,out9,out10,out11,out12,out13,out14,out15; wire 23:0 wr_addr_s;T8 t0(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.dat a(data),.ts(hw0);T8 t1(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.dat a(

46、data),.ts(hw1);T8 t2(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.dat a(data),.ts(hw2);T8 t3(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.dat a(data),.ts(hw3);T8 t4(.data_in(data_in),.clk(clk),.rst(rst),.

47、wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.dat a(data),.ts(hw4);T8 t5(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.dat a(data),.ts(hw5);T8 t6(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.dat a(

48、data),.ts(hw6);T8 t7(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.dat a(data),.ts(hw7);T8 t8(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.dat a(data),.ts(hw8);T8 t9(.data_in(data_in),.clk(clk),.rst(rst),.

49、wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.dat a(data),.ts(hw9);T8 t10(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.d ata(data),.ts(hw10);T8 t11(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.d a

50、ta(data),.ts(hw11);T8 t12(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.d ata(data),.ts(hw12);T8 t13(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.d ata(data),.ts(hw13);T8 t14(.data_in(data_in),.clk(clk),.r

51、st(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.d ata(data),.ts(hw14);T8t15(.data_in(data_in),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.d ata(data),.ts(hw15);mux_sms(.hw0(hw0),.hw1(hw1),.hw2(hw2),.hw3(hw3),.hw4(hw4),.hw5(hw5),.hw6(hw6),.hw7(hw7),.h w8(

52、hw8),.hw9(hw9),.hw10(hw10),.hw11(hw11),.hw12(hw12),.hw13(hw13),.hw14(hw14),.hw15( hw15),.out0(out0),.out1(out1),.out2(out1),.out3(out3),.out4(out4),.out5(out5),.out6(out6),. out7(out7),.out8(out8),.out9(out9),.out10(out10),.out11(out11),.out12(out12),.out13(out13),.out14 (out14),.out15(out15),.sel0(

53、count_2564:0), .sel1(count_2564:0), .sel2(count_2564:0), .sel3(count_25 64:0), .sel4(count_2564:0), .sel5(count_2564:0), .sel6(count_2564:0), .sel7(count_2564:0) ,.sel8(count_2564:0),.sel9(count_2564:0),.sel10(count_2564:0),.sel11(count_2564:0),.sel12 (count_2564:0),.sel13(count_2563:0),.sel14(count

54、_2563:0),.sel15(count_2563:0);s_ram srom0(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out0), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou0);s_ram srom1(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out1),.rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou1)

55、;s_ram srom2(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out2),.rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou2);s_ram srom3(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out3), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou3);s_ram srom4(.wr_clk(clk),.wr

56、_en(wr_en),.wr_addr(count_256),.data_in(out4), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou4);s_ram srom5(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out5), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou5);s_ram srom6(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_25

57、6),.data_in(out6),.rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou6);s_ram srom7(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out7), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou7);s_ram srom8(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out8), .rd_clk(cl

58、k),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou8);s_ram srom9(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out9), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou9);s_ram srom10(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out10), .rd_clk(clk),.rd_en(rd_en),.rd_addr(

59、data_out),.data_out(ou10);s_ram srom11(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out11), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou11);s_ram srom12(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out12), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou

60、12);s_ram srom13(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out13), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou13);s_ram srom14(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out14), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou14);s_ram srom15(.wr_c