10GBASER协议介绍课件

10GBASE-RAgenda10GBASE-Roverview

ImplementedinArria10TransceiverArria10PMAArchitectureArria10EnhancedPCSArchitectureArria10PLLsandClockNetworksDifferencesbetween10GBASE-Rand10GBASE-KR10GBASE-R10GBASE-RPHYistheEthernet-specificphysicallayerrunningata10.3125-GbpsdatarateasdefinedinClause49oftheIEEE802.3-2008specification.Thefollowingaretheobjectivesof10GBASE-R:•SupportthefullduplexEthernetMAC.•Provide10Gb/sdatarateattheXGMII.•SupportLANPMDsoperatingat10Gb/sandWANPMDsoperatingatSONETSTS-192c/SDHVC-4-64crate.•SupportcableplantsusingopticalfibercompliantwithISO/IEC11801:1995asspecifiedinClause52andClause68.•Allowforanominalnetworkextentofupto40km.•SupportaBERobjectiveof10–12.3Overviewofthe10GBASE-R4PhysicalMediumDependent(PMD)sublayerThePMDtranslatestheserializeddataofthePMAtoandfromsignalssuitableforthespecifiedmedium.InClause52：5InClause68：10GBASE-LRMPhysicalMediumAttachment(PMA)sublayerThePMAprovidesamedium-independentmeansforthePCStosupporttheuseofarangeofphysicalmedia.The10GBASE-RPMAperformsthefollowingfunctions:•MappingoftransmitandreceivedatastreamsbetweenthePCSorWISandPMAviathePMAserviceinterface.•Serialization(deserialization)ofbitsfortransmission(reception)ontheunderlyingserialPMD.•Recoveryofclockfromthereceiveddatastream.•MappingoftransmitandreceivebitsbetweenthePMAandPMDviathePMDserviceinterface.•OptionallyprovidesdataloopbackatthePMAserviceinterface.6WANInterfaceSublayer(WIS)TheWISprovidesamedium-independentmeansforthePCStooperateoverWANlinks.Itcreatesa10GBASE-Wencodingbyencapsulatingtheencodeddatasteamfromthe10GBASE-RPCSinframescompatiblewithSONETandSDHtransmissionformats.TheWISisspecifiedinClause50.7PhysicalCodingSublayer(PCS)ThePCSserviceinterfaceisthe10GigabitMediaIndependentInterface(XGMII),whichisdefinedinClause46.The10GBASE-RPCSprovidesallservicesrequiredbytheXGMII,includingthefollowing:•Encoding(decoding)ofeightXGMIIdataoctetsto(from)66-bitblocks(64B/66B).•Transferringencodeddatato(from)thePMAin16bittransfers.•WhenconnectedtoaWANPMD,deleting(inserting)idlestocompensatefortheratedifferencebetweentheMACandPMD.•DeterminingwhenafunctionallinkhasbeenestablishedandinformingthemanagemententityviatheMDIOwhenthePHYisreadyforuse.8PCSFunctionalblockdiagram9XGMIITransmissionNormalframetransmission10XGMIITransmissionTransmitErrorPropagation11XGMIIReceptionBasicframereception12XGMIIReceptionReceptionwitherror13Agenda10GBASE-Roverview

ImplementedinArria10TransceiverArria10PMAArchitectureArria10EnhancedPCSArchitectureArria10PLLsandClockNetworksDifferencesbetween10GBASE-Rand10GBASE-KR15Agenda10GBASE-Roverview

ImplementedinArria10TransceiverArria10PMAArchitectureArria10EnhancedPCSArchitectureArria10PLLsandClockNetworksDifferencesbetween10GBASE-Rand10GBASE-KRTransmitterThetransmittertakestheparalleldataandserializesittocreateahigh-speedserialdatastream.ThetransmitterportionofthePMAiscomposedofthetransmitterserializerandthetransmitterbuffer.TheserializerclockisprovidedfromthetransmitterPLL.17SerializerTheserializerconvertstheincominglow-speedparalleldatafromthetransceiverPCSorFPGAfabrictohigh-speedserialdataandsendsthedatatothetransmitterbuffer.18TransmitterBufferThetransmitterbufferincludesthefollowingcircuitry:•HighSpeedDifferentialI/O•Programmabledifferentialoutputvoltage(VOD)•Programmablefour-tappre-emphasiscircuitry•Powerdistributionnetwork(PDN)inducedinter-symbolinterference(ISI)compensation•Internalterminationcircuitry•ReceiverdetectcapabilitytosupportPCIExpressandQuickPathInterconnect(QPI)configurations19TransmitterBuffer20ReceiverThereceiverdeserializesthehigh-speedserialdata,createsaparalleldatastreamforeitherthereceiverPCSortheFPGAfabric,andrecoverstheclockinformationfromthereceiveddata.ThereceiverportionofthePMAiscomprisedofthereceiverbuffer,theclockdatarecovery(CDR)unit,andthedeserializer.21ReceiverBufferThereceiverbuffersupportsthefollowingfeatures:•Programmablecommonmodevoltage(VCM)•ProgrammabledifferentialOn-ChipTermination(OCT)•SignalDetector•ContinuousTimeLinearEqualization(CTLE)•VariableGainAmplifiers(VGA)•AdaptiveParametricTuningEngine•DecisionFeedbackEqualization(DFE)•On-DieInstrumentation(ODI)22ReceiverBuffer23ClockDataRecovery(CDR)UnitThePMAofeachchannelincludesachannelPLLthatyoucanconfigureasareceiverclockdatarecovery(CDR)forthereceiver.YoucanalsoconfigurethechannelPLLofchannels1and4asaclockmultiplierunit(CMU)PLLforthetransmitterinthesamebank.24DeserializerThedeserializerblockclocksinserialinputdatafromthereceiverbufferusingthehigh-speedserialrecoveredclockanddeserializesthedatausingthelow-speedparallelrecoveredclock.25Agenda10GBASE-Roverview

ImplementedinArria10TransceiverArria10PMAArchitectureArria10EnhancedPCSArchitectureArria10PLLsandClockNetworksDifferencesbetween10GBASE-Rand10GBASE-KRPCSTransmissioninClause4927TX_FIFOInPhaseCompensationmode,theTXFIFOdecouplesphasevariationsbetweentheFPGAfabricandtransceiverclockdomains.Inthismode,readandwriteoftheTXFIFOcanbedrivenbyclocksfromasynchronousclocksourcesbutmustbesamefrequency.Youcanusetx_coreclkin(FPGAfabricclock)ortx_clkout(TXparallellowspeedclock)toclockthewritesideoftheTXFIFO.2864B/66BEncoderThe64B/66BencoderisusedtoachieveDC-balanceandsufficientdatatransitionsforclockrecovery.Itencodes64-bitXGMIIdataand8-bitXGMIIcontrolinto10GBASE-R66-bitcontrolordatablocksinaccordancewithClause49oftheIEEE802.3-2008specification.The66-bitencodeddatacontainstwooverheadsyncheaderbitsthatthereceiverPCSusesforblocksynchronizationandbit-errorrate(BER)monitoring.Thesyncheaderis01fordatablocksand10forcontrolblocks.Syncheadersarenotscrambledandareusedforblocksynchronization.(Thesyncheaders00and11arenotused,andgenerateanerrorifseen.)Theremainderoftheblockcontainsthepayload.Thepayloadisscrambledandthesyncheaderbypassesthescrambler.2964B/66Bblockformats30ScramblerThescramblerrandomizesdatatocreatetransitionstoDC-balancethesignalandhelpCDRcircuits.Thescramblerusesax58+x39+1polynomial.31TXGearboxTheTXgearboxadaptsthePCSdatawidthtothesmallerbuswidthofthePCS-PMAinterface(GearboxReduction).Itsupportsdifferentratios(FPGAfabric-PCSInterfaceWidth:PCS-PMAInterfaceWidth)suchas66:32,66:40,64:32,40:40,32:32,64:64,67:64,and66:64.Thegearboxmuxselectsagroupofconsecutivebitsfromtheinputdatabusdependingonthegearboxratioandthedatavalidcontrolsignals.32TXBitslipTheTXgearboxalsohasabitslippingfeaturetoadjustthedataskewbetweenchannels.TheTXparalleldataisslippedontherisingedgeoftx_enh_bitslipbeforeitispassedtothePMA.ThemaximumnumberofthesupportedbitslipsisPCSdatawidth-1andtheslipdirectionisfromMSBtoLSBandfromcurrenttopreviousword.33PCSReceptioninClause4934RXGearboxTheRXgearboxadaptsthePMAdatawidthtothelargerbuswidthofthePCSchannel(GearboxExpansion).Itsupportsdifferentratios(PCS-PMAinterfacewidth:FPGAfabric–PCSinterfacewidth)suchas32:66,40:66,32:67,32:64,40:40,32:32,64:64,67:64,and66:64andabitslippingfeature.35RXBitslipRXbitslipisengagedwhentheRXblocksynchronizerorrx_bitslipisenabledtoshiftthewordboundary.OntherisingedgeofthebitslipsignaloftheRXblocksynchronizerorrx_bitslipfromtheFPGAfabric,thewordboundaryisshiftedbyoneserialbitor1UI.Eachbitslipremovestheearliestreceivedbitfromthereceiveddata.36BlockSynchronizerTheblocksynchronizerdeterminestheblockboundaryofa66-bitwordinthecaseofthe10GBASE-Rprotocol.Theincomingdatastreamisslippedonebitatatimeuntilavalidsynchronizationheader(bits65and66)isdetectedinthereceiveddatastream.Afterthepredefinednumberofsynchronizationheaders(asrequiredbytheprotocolspecification)isdetected,theblocksynchronizerassertsrx_enh_blk_lock(blocklockstatussignal)tootherreceiverPCSblocksdownthereceiverdatapathandtotheFPGAfabric.37DescramblerThedescramblerblockdescramblesreceiveddatatoregenerateunscrambleddatausingthex58+x39+1polynomial.3864B/66BDecoderThe64B/66Bdecoderreversesthe64B/66Bencodingprocess.39RXFIFOIn10GBASE-Rmode,theRXFIFOoperatesasaclockcompensationFIFO.Whentheblocksynchronizerachievesblocklock,dataissentthroughtheFIFO.Idleorderedsets(OS)aredeletedandIdlesareinsertedtocompensatefortheclockdifferencebetweentheRXlowspeedparallelclockandtheFPGAfabricclock(±100ppmforamaximumpacketlengthof64,000bytes).40Agenda10GBASE-Roverview

ImplementedinArria10TransceiverArria10PMAArchitectureArria10EnhancedPCSArchitectureArria10PLLsandClockNetworksDifferencesbetween10GBASE-Rand10GBASE-KRPLLsandClockNetworks42TransmitPLLTransmitPLLRecommendationBasedonDataRates43x1ClockLinesThex1clocklinesroutethehighspeedserialclockoutputofaPLLtoanychannelwithinatransceiverbank.Thelowspeedparallelclockisthengeneratedbythatparticularchannel'slocalclockgenerationblock(CGB).Non-bondedchannelconfigurationsusethex1clocknetwork.44x6ClockLinesThex6clocklinesroutetheclockwithinatransceiverbank.Thex6clocklinesaredrivenbythemasterCGB.Forbondedconfigurationmode,thelowspeedparallelclockoutputofthemasterCGBisusedandthelocalCGBwithineachchannelisbypassed.Fornon-bondedconfigurations,themasterCGBalsoprovidesahighspeedserialclockoutputtoeachchannelwithoutbypassingthelocalCGBwithineachchannel.45xNClockLinesThexNclocklinesroutethetransceiverclocksacrossmultipletransceiverbanks.ThemasterCGBdrivesthex6clocklinesandthex6clocklinesdrivethexNclocklines.Forbondedconfigurations,thelowspeedparallelclockoutputofthemasterCGBisused,andthelocalCGBwithineachchannelisbypassed.Fornon-bondedconfigurations,themasterCGBprovidesahighspeedserialclockoutputtoeachchannel.46Agenda10GBASE-Roverview

ImplementedinArria10Transce