数字集成电路：时序问题

1数字集成电路

-电路、系统与设计时序问题2同步互连3时序

定义4锁存器参数DClkQDQClktc-qtholdPWmtsutd-qDelayscanbedifferentforrisingandfallingdatatransitionsT5寄存器参数DClkQDQClktc-qtholdTtsuDelayscanbedifferentforrisingandfallingdatatransitions6时钟不确定性7时钟非理想化时钟偏差集成电路中一个时钟翻转的到达时间在空间上的差别通常称为时钟偏差时钟抖动指在芯片的某一个定点上的周期发生暂时的变化周期至周期抖动(短期)tJS长期tJL脉宽的差异性对各种灵敏时钟很重要8时钟偏差和抖动偏差和抖动都影响有效时钟周期只有偏差影响边缘路径ClkClktSKtJS9时钟偏差#ofregistersClkdelayInsertiondelayMaxClkskewEarliestoccurrence

ofClkedgeNominal–

/2Latestoccurrence

ofClkedgeNominal+

/2

10正时钟偏差和负时钟偏差11正时钟偏差12负时钟偏差13时序约束最小周期:T-=tc-q+tsu+tlogic接受沿到达早就有不好情况发生(positive)14时序约束维持时间约束:t(c-q,cd)+t(logic,cd)>thold+Worstcaseiswhenreceivingedgearriveslate

Racebetweendataandclock15抖动的影响16最长逻辑路径

边缘触发系统ClkTTSUTClk-QTLMLatestpoint

oflaunchingEarliestarrival

ofnextcycleTJI+d17时钟约束

边缘触发系统Iflaunchingedgeislateandreceivingedgeisearly,thedatawillnotbetoolateif:最小周期由通过逻辑的最大延时决定Tc-q+TLM+TSU<T–TJI,1–TJI,2-dTc-q+TLM+TSU+d+2TJI<T偏差是正向或是反向18最短路径ClkTClk-QTLmEarliestpoint

oflaunchingDatamustnotarrive

beforethistimeClkTHNominal

clockedge19时钟约束

边缘触发系统最小逻辑延时下降沿早来接受沿晚到:Tc-q+TLM–TJI,1<TH+TJI,2+dTc-q+TLM<TH+2TJI+d20怎样计算时钟偏差?21基于触发器的时序触发器逻辑ff=1f=0触发器延时偏差逻辑延时TSUTClk-QRepresentationafter

M.Horowitz,VLSICircuits1996.22触发器和动态逻辑f=1f=0LogicdelayTSUTClk-Qf=1f=0LogicdelayTSUTClk-QPrechargeEvaluateEvaluatePrechargeFlip-flopsareusedonlywithstaticlogic23锁存器时序DClkQtD-QtClk-QWhendataarrivestotransparentlatchWhendataarrivestoclosedlatchDatahastobe‘re-launched’Latchisa‘soft’barrier24锁存器的单相时序锁存器逻辑fClkPPWTsklTsklTsktTskt25基于锁存器的设计L1锁存器逻辑逻辑L2锁存器f

L1latchistransparent

whenf=0

L2latchistransparent

whenf=126锁存式时钟控制27基于锁存器的时序L1LatchLogicLogicL2Latchff=1f=0L1latchL2latchSkewCantolerateskew!LongpathShortpathStaticlogic28时钟分配Clockisdistributedinatree-likefashionH-tree29H数时钟[Restle98]30网格结构系统31例:DECAlpha211643221164时钟2phasesinglewireclock,distributedglobally2distributeddriverchannelsReducedRCdelay/skewImprovedthermaldistribution3.75nFclockload58cmfinaldriverwidthLocalinvertersforlatchingConditionalclocksincachestoreducepowerMorecomplexracecheckingDevicevariationtrise=0.35ns

tskew=150pstcycle=3.3nsClockwaveformLocationofclockdriverondiepre-driverfinaldrivers3334Alpha处理器的时钟偏差352Phase,withmultipleconditionalbufferedclocks2.8nFclockload40cmfinaldriverwidthLocalclockscanbegated“off”tosavepowerReducedload/skewReducedthermalissuesMultipleclockscomplicateracecheckingtrise=0.35nstskew=50pstcycle=1.67nsEV6(Alpha21264)时钟600MHz–0.35micronCMOSGlobalclockwaveform3621264时钟37EV6时钟分布情况GCLKSkew(atVdd/2Crossings)ps5101520253035404550ps300305310315320325330335340345GCLKRiseTimes(20%to80%Extrapolatedto0%to100%)38EV7时钟层次+widelydisperseddrivers+DLLscompensatestaticandlow-frequencyvariation+dividesdesignandverificationeffort-DLLdesignandverificationisaddedwork+tailoredclocksActiveSkewManagementandMultipleClockDomains

39自定时电路设计Functionsofclockinsynchronousdesign1)Actsascompletionsignal2)EnsuresthecorrectorderingofeventsTrulyasynchronousdesign2)Orderingofeventsisimplicitinlogic1)CompletionisensuredbycarefultiminganalysisSelf-timeddesign1)Completionensuredbycompletionsignal2)Orderingimposedbyhandshakingprotocol40流水线的同步数据通路41自定时的流水线数据通路42延时仿真43完成信号的电路44DCVSL的完成信号PDNB0PDNIn1In1In2In2B1StartStartVDDVDDDoneB0B145自定时加法器46利用电流检测产生完成信号47两相位握手协议48单元逻辑–Muller-C单元492相位握手协议Advantage:FAST-minimal#ofsignalingevents(importantforglobalinterconnect)Disadvantage:edge-sensitive,hasstate50例:自定时FIFO512相位协议52例From[Horowitz]53例54例55例564相位握手协议574相位握手协议58自复位逻辑59时钟延时多米诺60同步器-异步接口61同步器和判断器判断器:Circuittodecidewhichof2eventsoccurredfirst同步器:Arbiterwithclockfasoneoftheinputs问题:CircuitHAStomakeadecisioninlimitedtime-whichdecisionisnotimportant注意:ItisimpossibletoensurecorrectoperationBut,wecandecreasetheerrorprobabilityattheexpenseofdelay62一个简单的同步器•在时钟上升沿进行时钟采样•锁存器最终会解决信号估值,但是…会用很多时间!63同步器:输出变化轨迹64信号斜率的线性近似65例66噪声的影响Lowamplitudenoisedoesnotinfluencesynchronizationbehavior67典型的同步器用延迟线2相位时钟电路68串连