集成电路专业英语 课件 12 CMOS and FinFET Technology

12CMOSandFinFETTechnologyIntroductiontoCMOSTechnologyCMOSstandsforComplementaryMetal-Oxide-Semiconductor.Usesbothn-type(NMOS)andp-type(PMOS)transistorsinthesamecircuit.Keyadvantagesincludeultra-lowstaticpower,highnoiseimmunity,andefficientcircuitdesign.CMOSisthedominanttechnologyforlow-power,high-densitydigitalICs.CMOSFabricationTechnologiesN-well/P-welltechnology:simplestandmostcommonapproach.Twinwell(twintub)technology:independentoptimizationofNMOSandPMOS.Silicon-on-Insulator(SOI):insulatingsubstrateforsuperiorperformanceandisolation.TwinWellTechnology:IndependentOptimizationUsesn+orp+substratewithalightlydopedepitaxiallayer.Bothn-wellandp-wellareformedindependentlyontheepi-layer.Allowsseparatetuningofthresholdvoltage,bodyeffect,andtransconductance.Avoidsunbalanceddrainparasiticsseeninsingle-welltechnologies.Silicon-on-Insulator(SOI)TechnologyUsesaninsulatinglayer,typicallySiO₂,insteadofbulksilicon.Athinsiliconlayerisbuiltontopoftheinsulator.Advantagesincludelatch-upimmunity,lowerparasiticcapacitance,andhigherspeed.Highermanufacturingcost,justifiedfordeepsubmicrondevices.N-wellCMOSTechnology:TheIndustryStandardIndustryshiftedfromP-welltoN-wellCMOS.Electronshavehighermobilitythanholes.NMOSisbuiltinp-typesubstrate;PMOSisbuiltinsidethen-well.TheCMOSInverter:AProcessExampleCMOSinverterillustratesthefabricationsequence.ConsistsofNMOSandPMOSconnectedbetweenVDDandGND.Basicprocessrequiressixphotomasks:N-well,poly,n+,p+,contact,metal.N-wellFabricationSequence(Mask1)Growpadoxideonp-typewaferandpatternphotoresist.Etchexposedoxideandstripresist.Formn-wellbyionimplantationordiffusion,thenstrippadoxide.Gate&Source/DrainFormation(Masks2–4)Gateformation:growgateoxide,depositandpatternpolysilicon.N-diffusion:patternoxideandperformn+implantationforNMOS.P-diffusion:patternoxideandperformp+implantationforPMOS.InterconnectFormation(Masks5–6)Depositinterlayerdielectricandetchcontactholes.Sputtermetallayer(traditionallyaluminum).Patternmetaltoforminterconnectingwires.TheScalingLimit:EnterFinFETPlanarCMOSbelow~20nmsuffersfromshort-channeleffects.Gatelosescontrol,causingleakagecurrentandpoorswitching.FinFETintroducesa3Dfin-likechannelstructure.FinFET:A3DTransistorArchitectureChannelisformedinaverticalsiliconfin.Gatewrapsaroundthreesidesofthefin(tri-gate).Providessuperiorelectrostaticcontrolandreducedleakage.Adoptedat14nm,10nm,and7nmtechnologynodes.BulkFinFETFabricationFlowPatternandanisotropicallyetchsilicontoformverticalfins.FillfingapswithoxideandplanarizeusingCMP.Recessoxideandformgateoxideandgateelectrode.KeyTechnicalTermsEpitaxiallayer:crystallinelayergrownwithsamecrystalstructure.Latch-up:parasiticthyristoreffectcausingCMOSfailure.Sheetresistance:resistancepersquareofathinfilm.Thresholdvoltage(Vt):minimumgatevoltageforconduction.Electrostaticcontrol:gate’sabilitytocontrolchannelcurrent.Summary:TheTechnologyEvolutionCMOSisthefoundationofmoderndigital