DDR3 SDRAM的IP核调取流程

DDR3SDRAM的IP核调取流程

学完SDRAM控制器后,可以感受到SDRAM的控制器的书写是十分麻烦的，

因此在xilinx一些FPGA芯片内已经集成了相应的IP核来控制这些SDRAM,所

以熟悉此类IP核的调取和使用是非常必要的。下面我们以A7的因R3IP核作

为例子进行IP核调取。

DDR3是IP软核，什么是软核呢？软核就是使用查找表，寄存器搭建出来的

IP核。需要占用FPGA的逻辑。

一、DDR3SDRAMIP核建立流程

1、在工程建好之后，可以点即IPCatalog来建立相应的IP,具体界面如

图所示。

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显示项目管理操作切换到项目管理器环境

在搜索区搜索mem”y,然后找到如下图所示的选项，双击。

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设置

2、点击next

project_l-[C:/Users/AdminiJQXilinxMemoryInterfaceGenerator

FileEditFlowJools

MemoryInterfaceGenerator

REFERENCE

DESIGNniTheMemoryInterfaceGenerator(MIG)ere：

/VHDLRTLsourcecode,pin-outanddesign

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VivadoProjectOptions

7PROJECTMANAGER

ThisGUIincludesallconfigurableoptioi

*Settingsthatsomeoftheoptionsselectedinthe

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SelectedVivadoProjectOptions：

LanguageTemplates

卓IPCatalog

FPGAFamily

FPGAPart

▼IPINTEGRATOR

SpeedGrade

CreateBlockDesignMemorySynthesisTool

DesignEntry

OpenBlockDesign

InterfaceIfanyoftheseoptionsareincorr(

GenerateBlockDesignrestartHIG.ThisversionofMIGi<

versionsofVivado.

ySIMULATIONGenerator

RunSimulation

▼RTLANALYSIS

>OpenElaboratedDesign

▼SYNTHESIS

►RunSynthesisEXILINX

>OpenSynthesizedDesigi

UserGuideVersionInfo

CustomizeIP,mig_7series_0,...(

3、定义器件名，选择控制器个数。控制器个数我们选择1个，点击next。

Eproject」-[C:/Users/AdminiqXilinxMemoryInterfaceGenerator

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FlowNavigator▼

7PROJECTMANAGER

*Settings

AddSources

LanguageTemplates

fIPCatalog

IPINTEGRATOR

CreateBlockDesign

OpenClockDesign

GenerateBlockDesign

SIMULATION

RunSimulation

RTLANALYSIS

>OpenEiaooratedDesign

SYNTHESIS

ARunSynthesis

>OpenSynthesizedDesigi

CustomizeIP'mig_7series_0'...

注：AXI4Interface,就选择的是AXI格式的MIG核，不勾是传统的接且

信号格式。

4、进入到如图所示的界面，如果使用的芯片相同，则可以选择，若没有,

可以不选，继续点击next。

qXilinxMemoryInterfaceGenerator

PinCompatible?PGAs

REFERENCE

DESIGNPHPinCompatibleFPGAsincludealldeviceswiththesamepackageandspee

withthesamepackagedonothavethesamebondedpins.ByselectingPi

commonbetween:.hetargetdeviceandallselecteddevices.Usethedefa

targetpartischanged,usetheappropriateXDCinthecompatible_ucff

nowandlateradifferentFPGAisused,thegeneratedXDCnay

nayberequired.MIGonlyensuresthatMIGgeneratedpinoutiscompi

Unselecteddeviceswillnotbeconsideredforcompatibilityduringthe

PinConpatibleFPGAs

Ablanklistindicatesthattherearenocompatiblepartsexistforthe

MemorySelection

Notethatdifferentpartsinthesamepackage*illhavedifferentinter

appropriatelyintheControllerOptionspagewhendifferentpartsinth

ControllerOptionsinformation.

AXIParameterTargetFPGAxc7a75t-fgg484-2

MemoryOptionsPinCompatibleFPGAs

/artix7

FPGAOptions

/7a

ExtendedFPGAOpti«ns□xc7a35t-fgg484

□xc7a50t-fgg484

IOPlanningOptions

□xc7al00t-fgg484

BankSelect!on

]xc7al5t-fgg484

SystemSignalsSelection

Summary

SimulationOptions

PCBInformation

DesignNotes

£XILINX

UserGuideVersionInfo

5、进入到选取控制器类型的界面，由此我们选择DDR3,点击next。

qXilinxMemoryInterfaceGenerator

MemorySelection

REFERENCE

DESIGNOJSelectthetypeofmemoryinterface.PleaserefertotheUserGuidefor

family.Thelistbelowshowscurrentlyavailableinterface(s)forthes;

SelecttheControllerType：

PinConpatibleFPGAsQDDR3SDRAM

DDR2SDRAM

LPDDR2SDRAM

ControllerOpti

AXIParaneter

MemoryOptions

FPGAOptions

ExtendedFPGAOptions

10PlanningOptions

BankSelection

SystenSignalsSelection

Sunnary

SimulationOptions

PCBInformation

DesignNotes

EXILINX

UserGuideVersionInfo

6、进入到DDR3SDRAM相应参数的界面，我们首先选择的是DDR3的工作频

率设置为400MHZ。因为开发板上的供电电压为1.35V,所以我们在此处设置为

1.35VO设置DDR3的总线位宽是16位的。

qXilinxMemoryInterfaceGenerator

REFERENCEOptionsforController0—DDR3SDRAM

DESIGN口J

ClockPeriod：Choosetheclockperiodforthedesiredfrequency.Th

FPGAspeedgrade.RefertotheUserGuideformoreinformation.

vTQachieireoptinwnresourceutjJsratjvji,aaZafaZutfefaul

per*。£PleasecositacfXilinxTeC-JEUIJc&1Supportforf^rt

PHItoControllerClockRatio：SelectthePMYtoMemoryControll

PinCompatibleFPGAs”operatesateither1/4or1/2ofthePMYrate.TheselectedMemoryCl

¥ccaux_io：Vccaux_iomustbesetto2,OYintheHighPerformanceba:

HenorySelect!on/banks.NotethatVccaux_ioiscommontogroupsofbanks.Consultthe

information.

ControllerOption;

AXIParameterMemoryType：Selectthememorytype.Type(s)markedwithawarning

MemoryPart：Selectthememorypart.Part(s)markedwithawarning

HenoryOptionsequivalentpartorcreateapartusingthe“CreateCustomPart“butto

notsupportedforRLDRAMII.

FPGAOptions

MemoryVoltage：SelecttheVoltageoftheMemorypartselected.

ExtendedFPGAOptions

DataWidth：SelecttheDataWidth.PartsmirkedwithQwarningsymb

10PlaimingOptions

BankSelectionECC：MIGsupportsECCfor72bitdatawidthconfiguration.Tobeabl)

SystemSignalsSelectionDataMask：EnableordisablethegenerationofDataMask(DM)pinsi

selectedhasDMpins.Uncheckthisboxtonotusedatamasksandsave

willnotuseDataMask.

Summary

SimulationOptions

PCBInfornation

Hnnth»rnfRankIIArhi'Thisparamatarifh*nnmharnfhan'

DesignHolesMote：Settingalowervaluewillresultinlowerresourceutilization,

ORDERING：Normalmodeallowsthememorycontrollertoreordercommar

thecontrollertoexecutecommandsintheexactorderreceived.

：2Gb,xl6,row：14,col：10bark：3,databitsperstrobe

CXILINXMemoryDetails,

UserGuideVersionInfo

位宽的计算：400*2*16=12.8Gbps带宽

400是控制器PHY的时钟,2是DDR双沿采样，16是16bit位宽，半双工,

所以考虑读写的情况，平均分配的话每个操作占有6.Kbps的理论带宽。

(1)Clockperiod:通过周期调整DDR3工作时钟。

(2)4:1和2:1部分，是选择用户的工作时钟。

4:1表示DDR3工作时钟400M情况下用户时钟为100Mo

2：1表示DDR3工作时钟400M的情况下用户时钟为200M。

(3)memorypart的意思是选择DDR3器件的型号。

(4)NumberofBankMachines:意思是bank的数量。

(5)Datamask：代表的是数据淹模

7、输入IP核的时钟设置为200Mhz,我们将200Mhz通过PLL倍频产生

400MHZ的时钟,然后给PHY芯片。

qXilinxMemoryInterfaceGenerator

MemoryOptionsforController0-DDR3SDXAM

REFERENCE

DESIGNQj

PinConpatibleFPGAs

HemorySelection

ControllerOptions

AXIParameter

MemoryOptions

FPGAOptions

ExtendedFPGAOptions

10PlanningOptions

BankSelection

SystemSignalsSelection

Summary

SimulationOptions

PCBInformation

DesignMotes

£XILINX

UserGuideVersionInfo

(1)inputclockperiod：IP核的工作时钟,常用时钟50M、200M必须直

接连板子。

(2)readbur^ttypeandlength表示：数据顺序。

(3)memoryaddressmappingselecUon表示：地址类型。

8、设置控制系统时钟和参考时钟

系统时钟有single_ended、deferential和nobuffer三种，

single_ended为来源于引脚的单端时钟,diferential为差分时钟,nobuffer

为来源于FPGA内部的时钟。参考时钟有4种，其中三种也为single_endcd、

deferential和nobuffer,另外一种为usesystemclock,注意：只有在

systemclock时钟频座为199Mhz~201Mhz时,参考时钟才能存在usesystem

clock选项。

注1：如果选择参考时钟,如果选择200Mhz系统时钟,可以不选参考时钟

育接使用系统时钟作为参考时钟.

注2：systemresetpolarity意思是选择复位高低有效。

vXilinxMemoryInterfaceGenerator

REFERENCESystemClock

DESIGNQJ

Choosethedesiredinputclockconfiguration.DesignclockcanbeDifft

SystemClock

ReferenceClock

Choosethedesiredreferenceclockconfiguration.ReferenceclockcanI

PinCompatibleFPGAs

ReferenceClock

HenorySelection

SystemResetPciarity

ControllerOptionsChoosethedesiredSystemResetPolarity.

AXIParameterSystemResetPolarity

MenoryOptionsDebugSignalsControl

ThisfeatureallowsvariousdebugsignalspresentintheIPtobemonii

FPGAOptions

EnablingthisfeaturewillconnectallthedebugsignalstotheChipScc

groundedsothatuserscanreplacethegroundedsignalswiththerequii

ExtendedFPGAOptions

DebugSignalsforMenoryController

IOPlanningOptions

ThisselectsthevalueofSampleDatadepthforChipscopeILAusedinI

BankSelection

SampleDataDepth

SystemSignalsSelection

InternalVref

Summary

InternalVrefcanbeusedtoallowtheuseoftheVrefpinsasnormal]

inputsareused.Thissettinghasnoeffectonbankswithonlyoutputs.

SimulationOptions

InternalVref

PCBInfornation

10PowerReduction

DesignVotesSignificantlyreducesaverage10powerbyautomaticallydisablingDQ/DC

IOPowerReduction

XADCInstantiation

ThememoryinterfaceusesthetemperaturereadingfromtheXADCblock1

£XILINXblockperdevice.IftheXADCisnotcurrentlyusedanywhereinthede:

UserGuideVersionInfo

9、点击next,勾选第二项，再次可以直接导入DDR3SDRAM的引脚信息，

前提是引脚约束文件已经存在，引脚约束文件可以是ucf和x”类型。然后点

击如下两个图标找到ucf/xdc的路径，选择对应的约束文件，点击打开，之后

点击validate来确认约束文件有效。

qXilinxMemoryInterfaceGenerator

PinSelectionF*rController0-DDR3SDRAM

REFERENCE

DESIGNQJ

SignalNameBankNumber

1ddr3_dq[0]35

2ddr3_dq[l]35

PinCompatibleFPGAs3ddr3_dq[2]35

MemorySelection4ddr3_dq[3]35

ControllerOptions5ddr3_dq[4]35

AXIParameter6ddr3_dq[5]35

MemoryOptions7ddr3_dq[6]35

FPGAOptions8ddr3_dq[7]35

ExtendedFPGAOptions9ddr3_dq[8]35

10PlanningOptions10ddr3_dq[9]35

PinSelection11ddr3_dq[10]35

SystenSignalsSelection12ddr3_dq[ll]35

Summary13ddr3_dq[12]35

SimulationOptions14ddr3_dq[13]35

PCBInfornation15ddr3_dq[14]35

DesignNotes16ddr3_dq[15]35

17ddr3_dm[0]35

18ddr3_dm[l]35

£XILINXIWFO:Validati«nsuccessful.PressNexttoproceed.

UserGuideVersionInfo

10、默认点击next,剩余的直接点击next就可以了。最后gengera及生成

DDR3IP核。

XilinxMemoryInterfaceGenerator

SystemSignalsSelection

REFERENCE

DESIGNHlSelectthesystempinsbelowappropriatelyfortheinterface.Customizat

andPinrules.

SystemClockandReferenceClockpinselectionswillnotbevisibleift

SystemClockPinSelection

PinCoapatibleFPGAsThesys_clkisusedasthesystemclockforthememoryinterface.T1

bestperformance.Thiasxgnolshouldbeintheaddress/controlbank,