VerilogHDL负责数字电路设计（AI助学版）课件

16.3时序逻辑库单元时序逻辑库单元主要包括两大类型：电平敏感的锁存器时钟边沿敏感的D触发器由于VerilogHDL没有内置的时序逻辑原语，因此需要使用用户自定义原语（UDP）或门级建模来实现时序逻辑器件16.3.1电平敏感库单元`timescale1ns/1ps`celldefinemoduleTLATX1(Q,QN,D,G);outputQ,QN;inputD,G;regNOTIFIER;supply1xRN,xSN;supply1dSN,dRN;udp_tlatI0(n0,D,clk,xRN,xSN,NOTIFIER);bufI1(Q,n0);notI2(QN,n0);notI3(clk,G);bufI4(flgclk,G);andI5(SandR,xSN,xRN);andI6(SandRandCLK,xSN,xRN,flgclk);specifyspecparam//timingparameterstplh$D$Q=1.0,tphl$D$Q=1.0,tplh$D$QN=1.0,后缀X1的含义为单元TLAT中的一种器件，数字“1”表示器件的一个规格，其值越大，对应器件的面积尺寸越大。GDQ[n+1]QN[n+1]100111100xQ[n]QN[n]tphl$D$QN=1.0,tplh$G$Q=1.0,tphl$G$Q=1.0,tplh$G$QN=1.0,tphl$G$QN=1.0,tsetup$D$G=1.0,thold$D$G=0.5,tminpwh$G=1.0,tperiod$G=1.0;//pathdelaysif(SandR)(posedgeG*>(Q+:D))=(tplh$G$Q,tphl$G$Q);if(SandR)(posedgeG*>(QN-:D))=(tplh$G$QN,tphl$G$QN);if(SandRandCLK)(D*>Q)=(tplh$D$Q,tphl$D$Q);if(SandRandCLK)(D*>QN)=(tplh$D$QN,tphl$D$QN);

//timingchecks$setuphold(negedgeG&&&(SandR==1),posedgeD,tsetup$D$G,thold$D$G,NOTIFIER);$setuphold(negedgeG&&&(SandR==1),negedgeD,tsetup$D$G,thold$D$G,NOTIFIER);$width(posedgeG&&&(SandR==1),tminpwh$G,0,NOTIFIER);$period(posedgeG&&&(SandR==1),tperiod$G,NOTIFIER);endspecifyendmodule//TLATX1`endcelldefine16.3.2边沿敏感库单元`timescale1ns/1ps`celldefinemoduleEDFFXL(Q,QN,D,CK,E);outputQ,QN;inputD,CK,E;regNOTIFIER;supply1xRN,xSN;supply1dRN,dSN;udp_edffI0(n0,D,CK,xRN,xSN,E,NOTIFIER);bufB1(Q,n0);notI1(QN,n0);andI2(flag,xRN,xSN);andI3(Dcheck,xSN,xRN,E);r：表示信号的上升沿，从低电平0跳到高电平1；f：表示信号的下降沿，从高电平1下降到低电平0。后缀XL表示为EDFF单元系列中的一种D触发器EDCKQ[n+1]QN[n+1]0xxQ[n]QN[n]10r0111r101xfQ[n]QN[n]specifyspecparamtplh$CK$Q=1.0,tphl$CK$Q=1.0,tplh$CK$QN=1.0,tphl$CK$QN=1.0,tsetup$D$CK=1.0,thold$D$CK=0.5,tsetup$CK$CK=1.0,thold$CK$CK=0.5,tsetup$E$CK=1.0,thold$E$CK=0.5,tminpwl$CK=1.0,tminpwh$CK=1.0,tperiod$CK=1.0;//pathdelaysif(Dcheck)(posedgeCK*>(Q+:D))=(tplh$CK$Q,tphl$CK$Q);if(Dcheck)(posedgeCK*>(QN-:D))=(tplh$CK$QN,tphl$CK$QN);//timingchecks$setuphold(posedgeCK&&&(Dcheck==1),posedgeD,tsetup$D$CK,thold$D$CK,NOTIFIER);$setuphold(posedgeCK&&&(Dcheck==1),negedgeD,tsetup$D$CK,thold$D$CK,NOTIFIER);$setuphold(posedgeCK&&&(flag==1),posedgeE,tsetup$E$CK,thold$E$CK,NOTIFIER);$setuphold(posedgeCK&&&(flag==1),negedgeE,tsetup$E$CK,thold$E$CK,NOTIFIER);$width(negedgeCK&&&(flag==1),tminpwl$CK,0,NOTIFIER);$width(posedgeCK&&&(flag==1),tminpwh$CK,0,NOTIFIER);$period(posedgeCK&&&(flag==1),tperiod$CK,NOTIFIER);endspecifyendmodule//EDFFXL`endcelldefineprimitiveudp_edff(out,in,clk,clr_,set_,en,NOTIFIER);outputout;inputin,clk,clr_,set_,en,NOTIFIER;regout;table//inclkclr_set_enNOT:Qt:Qt+10r?11?:?:0;//clockin01r1?1?:?:1;//clockin1?*??0?:?:-;//nochanges,notenabled*???0?:?:-;//nochanges,notenabled1*1???:1:1;//reducepessimism0*?1??:0:0;//reducepessimism?f????:?:-;//nochangesonnegedgeclk*b????:?:-;//nochangeswheninswitches1x1???:1:1;//nochangeswheninswitches0x?1??:0:0;//nochangeswheninswitches?b??*?:?:-;//nochangeswhenenswitches?x110?:?:-;//nochangeswhenenisdisabled???0??:?:1;//setoutput?b1*??:1:1;//coveralltransitionsonset_??1*0?:1:1;//coveralltransitionsonset_??01??:?:0;//resetoutput?b*1??:0