netfpga最新介绍学习资料PPT课件

1、1,从初次接触到熟练应用,杨卫 ,/,2,内容,初识NetFPGA 目标设计平台 开发系统搭建 近观NetFPGA 浅出Router架构 深入Router软硬件 Demo1: Reference Router 再会NetFPGA 开发实践之路 丰富的Projects 皆可NetFPGA Demo 2: 流量检测,3,NetFPGA2.1开发板,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,4,能否满足你的设计需求？

2、,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,FPGA器件 逻辑规模、I/O及专用资源 用户指南和数据手册 外部接口 4个千兆以太网口 PCI总线接口 2个SATA接口 存储器 4.5MB ZBT SRAM 64MB DDR2 DRAM 时钟资源 FPGA和SRAM支持125MHz DRAM支持200MHz,链接关系？,5,不仅仅是开发板,To gain a competitive edge To upgrade a desig

3、n To achieve greater margin To reduce design time and effort,PCI,CPU,Memory,开发板,PC with NetFPGA,运行于PC上的网络软件,带硬件加速的 网络设计平台,6,如何建立自己的开发系统？,7,获取硬件,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,PC 购买预装机 自己装配 推荐配置/foswiki/bin/vi

4、ew/NetFPGA/OneGig/Guide#List_of_PC_Components 千兆网卡 当前项目都是基于EXPI9402PT 其他网卡，比如TPLink8139,2U Server (Dell 2950),1U Server (Accent Technology, Inc),自己装配,8,安装软件,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,操作系统 Linux CentOS 4/5 http:/netfpga.o

5、rg/CentOS_Install.pdf 辅助工具安装 Perl安装包 Java安装包 CAD工具安装 ISE，Chipscope Pro Modelsim 存储器仿真模型 基础开发包安装 硬件设计、驱动及GUI 下载/beta/distributions,用户空间 Linux内核,NIC,GE,PCI-e,PCI,Browser & Video Client,GUI,GE,GE,GE,GE,GE,CAD Tools,可编程硬件,VI,VI,VI,VI,驱动,(eth1 . 2),(nf2c0 . 3),Web & VideoServer,9,总观NetFP

6、GA,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,10,深入浅出Reference Router,11,IP Router on NetFPGA,Switching,转发,路由表,路由协议,用户界面,Linux user-level processes,Verilog on NetFPGA 开发板,驱动程序,Packest,12,浅出Router架构,To gain a competitive edge To upgrade a

7、 design To achieve greater margin To reduce design time and effort,PCI,软件,NetFPGA,13,NFP目录结构（一）,NF2,bin,lib,projects,bitfiles,(运行仿真和设置环境变量的脚本),(所有的FPGA配置文件),(参考设计所有的软硬件源代码，包括C、Java、Perl及VerilogHDL等),(用户工程相关文件),14,NFP目录结构（二）,lib,C,java,Makefiles,Perl5,python,scripts,verilog,(驱动程序源代码),(用户界面源代码),(仿真和综合

8、的makefiles),(用于硬件仿真的通用库),(用于regression测试的通用库),(通用功能的脚本命令，比如启动RouterGUI),(参考设计Router的VerilogHDL源码),15,NFP目录结构（三）,projects,doc,include,regress,src,sw,synth,verif,(工程说明文档),(设计中的module列表和寄存器定义文件),(regression测试文件),(工程中新添加module的verilogHDL源代码),(工程的软件代码),(生成IP core对应的.xco文件和makefiles),(仿真测试的Perl文件),16,Rout

9、er硬件设计,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,最顶层module nf2_top 功能实现module nf2_top 主数据通路module input_arbiter output_port_lookup oq_queues 链路层module nf2c_mac_grp SRAM控制器 sram_arbiter 差异化module output_port_lookup,17,VerilgoHDL源代码,veril

10、og,common,cpci_bus,dma,nf2,io_queues,user_data_path,testbench,(宏定义文件，比如module寄存器位宽及地址),(cpci总线接口描述及PCI逻辑核,(DMA接口和包传输module),(最顶层module、rgmii接口及Router功能module),(Router链路层处理module),(主数据通路module及寄存器实现),(仿真测试task),还有user_data_path中的module,18,流水线,To gain a competitive edge To upgrade a design To achieve

11、greater margin To reduce design time and effort,输入队列 链路层实现 包缓冲 队列调度 选择一个RxQ Packets处理 包头检查 路由查找 输出缓冲 选择一个TxQ 包缓冲池 输出队列 链路层实现 包缓冲,19,module header,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,IP Hdr,Eth Hdr,0,0,0,Last word of packet,0 x10,L

12、ast Module Hdr,y,Module Hdr,x,包含Packets字长, 输入端口，输出端口等,Data Word (64 bits),Ctrl Word (8 bits),每个模块都可添加自己的module_header 前后级模块交换信息，比如处理结果。,20,Packets和Reg双数据通路,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,统一的外部接口和内部结构 模块化设计思路,21,Module间的单向操作,T

13、o gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,rdy信号 请求数据 data信号 64bits数据字 ctrl信号 8bits标记 wr信号 数据字有效,22,output_port_lookup外部接口,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,23,output

14、_port_lookup内部结构,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,24,HDL源码探究,第一 迅速定位某个module 脑海里有一张Router电路结构图 第二 想起某个module，脑海里是其电路结构 FSM、always等 第三 将算法和电路一一对应 理解module电路的可取之处,端口定义 output、input、寄存器接口及系统信号 线网和参数定义 module实例化 FSM描述 两段式,25,NetFPG

15、A驱动,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,寄存器读写 Packets传输 PCI设备初始化,26,驱动程序源代码,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,c,common,kernel,download,reg_access,switch,route

16、r,nic,(用于操控硬件设备的函数),(内核驱动程序),(下载配置文件的程序),(读写寄存器示例),(状态寄存器显示程序),(Router 相关的c程序),(用于统计Packets的树木等),27,如何访问硬件寄存器,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,从用户软件协议栈驱动程序NetFPGA板卡,PCI Bus,1.用户软件调用Write/Read函数； 2.启动驱动程序的ioctl；,28,操作硬件的接口函数,To

17、gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,板卡相关操作 nf2_probe函数和nf2_remove函数 nf2c_open函数和nf2c_release函数 寄存器读写 readReg和writeReg 网络设备和字符设备 Packets收发 nf2c_send函数 nf2c_rx函数,29,Router用户界面（一）,To gain a competitive edge To upgrade a design To achiev

18、e greater margin To reduce design time and effort,Router 硬件设计 电路结构,30,Router用户界面（二）,Router 配置界面,31,第一步 编译硬件,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,启动终端, cd to “NF2/projects/tutorial_router/synth” 运行 “make clean” 开始编译“make/ time make”

19、,32,第二步 启动界面,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,cd “NF2/projects/tutorial_router/sw” 运行: “tut_router_gui.pl” 启动Router用户界面,33,带给我们什么？,NetFPGA 带硬件加速的包处理系统 可扩展的包处理平台 Reference Router 用于数据包处理的通用电路库 用于仿真和系统操作的脚本及GUI 实用的regression test

20、s功能块,34,开发实践之路,35,在Router基础上的开发,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,FPGA,Memory,1GE,1GE,1GE,1GE,PCI,CPU,Memory,Java GUI,PW-OSPF,自己的 module,36,全新的系统开发,FPGA,Memory,1GE,1GE,1GE,1GE,PCI,CPU,Memory,设计 仿真 综合 下载,37,由浅入深,To gain a competi

21、tive edge To upgrade a design To achieve greater margin To reduce design time and effort,流量检测模块 包头 包内容 新的module Where How Module实现 外部接口 内部功能 Testbench 已有的一些task,38,硬件设计实现（一）,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,新建工程 cd： “ NF2/proje

22、cts” 推荐方式：copy tutorial_router修改工程名为traffic_mon 修改上层module 打开“NF2/projects/tutorial_router/src/user_data_path.v ” 添加module实例化和wire定义,39,硬件设计实现（二）,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,添加新的module 在“NF2/projects/traffic_mon/src” 添加寄存器

23、定义 打开“/NF2/lib/verilog/common/src21/ udp_defines ” 遵循原有的宏定义格式,40,软件设计,To gain a competitive edge To upgrade a design To achieve greater margin To reduce design time and effort,驱动程序 调用了寄存器读写接口 Java用户界面 可视化组件 事件响应函数,41,熟练应用不是终点,42,众多开源项目,经典应用 IP-Lookup with a Blooming Tree Array DFA-based Regular Expression Matching Packet Generator