姜书艳数字逻辑设计及应用14

1、1,Chapter 6 Combinational Logic Design Practices(组合逻辑设计实践),Documentation Standard and Circuit Timing (文档标准和电路定时) Commonly Used MSI Combinational Logic Device (常用的中规模组合逻辑器件),Digital Logic Design and Application (数字逻辑设计及应用),2,期中考试,时间： 5月11日 (周六) 19:00-21:00 范围： 第二章、第三章、第四章、第六章内容及有关补充内容 集中答疑时间： 5月11日（周

2、六） 8:30-11:30 14:30-17:30 地点：待定,3,实验课答疑验收通知,本周四（4月25日） 下午 2:30-5:30 地点：科A335,4,Decoder (译码器) Cascading Binary Decoders (译码器的级联) Realize a Logic Circuit by Using Decoder (利用译码器实现逻辑电路),Review of Last Class (内容回顾),Digital Logic Design and Application (数字逻辑设计及应用),5,BCD Decoder ( 二十进制译码器 ) Seven-Segment

3、Decoders(七段显示译码器),Review of Last Class (内容回顾),Digital Logic Design and Application (数字逻辑设计及应用),6,用译码器和逻辑门实现逻辑函数,F = (X,Y,Z) (1,3,5,6),Digital Logic Design and Application (数字逻辑设计及应用),A Class Problem ( 每课一题 ),7,6.5 Encoder（编码器）,1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1

4、 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1,2n Inputs,n Out- puts,Truth Table for a 8-to-3 Encoder,Digital Logic Design and Application (数字逻辑设计及应用),8,Encoder,N inputs with exactly one of them being set to 1, log2(n) outputs for encoding.,8,4

5、x2,4 x 2 encoder,9,Guarantee: The Inputs are asserted at most one at a time. (前提： 任何时刻只有一个输入端有效。),6.5 Encoder（编码器）,Truth Table for a 8-to-3 Encoder,Digital Logic Design and Application (数字逻辑设计及应用),10,A0 = I1 + I3 + I5 + I7,A1 = I2 + I3 + I6 + I7,A2 = I4 + I5 + I6 + I7,Trouble: When more than One Inp

6、uts are asserted? (问题：当某时刻出现多个输入有效？),Priority（优先级）,6.5 Encoder（编码器）,Truth Table for a 8-to-3 Encoder,Digital Logic Design and Application (数字逻辑设计及应用),ABCD = A,11,Priority Encoder(优先编码器),Change I0I7 to H0H7, Make Sure the Inputs are asserted at most one at a time. ( 将 I0I7 转换为 H0H7， 保证其中，任何时刻只有一个有效),

7、Highest-Priority ( 数大优先 ),6.5 Encoder（编码器）,Digital Logic Design and Application (数字逻辑设计及应用),12,Priority Encoder(优先编码器),H7 = I7 H6 = I6 I7 H5 = I5 I6 I7 H0 = I0 I1 I2 I6 I7 A2 = H4 + H5 + H6 + H7 A1 = H2 + H3 + H6 + H7 A0 = H1 + H3 + H5 + H7,Highest-Priority ( 数大优先 ),6.5 Encoder（编码器）,Digital Logic De

8、sign and Application (数字逻辑设计及应用),13,Priority Encoder(优先编码器),Change I0I7 to H0H7, Make Sure the Inputs are asserted at most one at a time. ( 将 I0I7 转换为 H0H7， 保证其中，任何时刻只有一个有效),Highest-Priority ( 数大优先 ),The IDLE Output is asserted if No Inputs are asserted. (如果没有输入有效，则 IDLE 为1 ) IDLE = I0 I1 I6 I7,6.5

9、Encoder（编码器）,Digital Logic Design and Application (数字逻辑设计及应用),14,图6-48 表6-27,The 74x148 Priority Encoder (优先级编码器74x148),Digital Logic Design and Application (数字逻辑设计及应用),15,2个74x148级联为164优先编码器,Digital Logic Design and Application (数字逻辑设计及应用),16,输入：由864，需8片74x148 每片优先级不同（怎样实现？） 保证高位无输入时，次高位才工作 高位芯片的EO

10、端接次高位芯片的EI端,用8-3优先编码器74x148级联为64-6优先编码器,片间优先级的编码 利用第9片74x148 每片的GS端接到第9片的输入端 第9片的输出作为高3位（RA5RA3）,片内优先级 片间优先级,输出：6位,8片输出A2A0 通过或门作为 最终输出的低3位 RA2RA0,Digital Logic Design and Application (数字逻辑设计及应用),17,分析判定优先级电路：（利用74x148 ） 8个_电平有效输入I0_LI7_L，_的优先级最高 地址输出A2A0，_电平有效 若输出AVALID高电平有效，则表示_,A2 A1 A0,AVALID,低,

11、I0_L,至少有一个输入有效,低,题6.53,Digital Logic Design and Application (数字逻辑设计及应用),18,设计判定优先级电路：（利用74x148 ） 8个输入I0I7高电平有效，I7优先级最高 地址输出A2A0，高电平有效 如果没有输入有效，为111且输出IDLE有效,题6.52,Digital Logic Design and Application (数字逻辑设计及应用),19,6.6 Three-State Devices (三态器件),Three-State Buffer (Three-State Driver) 三态缓冲器（三态驱动器）,F

12、igure 6-51,Three States: Active High(1) ，Active Low (0), Hi-Z (三种状态：高电平，低电平，高阻态）,Digital Logic Design and Application (数字逻辑设计及应用),20,6.6 Three-State Devices (三态器件),Three-State Device allow Multiple Sources to Share a Single “Party Line“ As long as Only One device “talk” on the Line at a time （三态器件允许

13、多个信号源共享单个“同线”， 条件是每次只有一个器件工作） (Figure 6-52),Digital Logic Design and Application (数字逻辑设计及应用),21,6.6 Three-State Devices (三态器件),Typical Three-State Devices are Designed So that they go into the Hi-Z state Faster than they come out of the Hi-Z state. （对典型的三态器件，进入高阻态比离开高阻态 的时间快）,Digital Logic Design an

14、d Application (数字逻辑设计及应用),22,6.6 Three-State Devices (三态器件),74x245：双向传输数据，低电平使能 DIR 决定传输方向,74x541：两个公共使能端，低电平使能， 施密特触发输入，输出不反相 （图6-54 6-55）,Standard SSI and MSI Three-State Buffer (标准SSI和MSI三态缓冲器),（图6-56 6-57）,Digital Logic Design and Application (数字逻辑设计及应用),23,冲突（fighting）,利用使能端进行时序控制,三态器件允许信号共享单个“

15、同线”（party line）,典型的三态器件，进入高阻态比离开高阻态快,Digital Logic Design and Application (数字逻辑设计及应用),24,Digital Logic Design and Application (数字逻辑设计及应用),Figure 6-53,25,Notation of Data Bus （数据总线的表示法）,图 655,Digital Logic Design and Application (数字逻辑设计及应用),26,Transfer Data in Either Directions By Using Three-State T

16、ransceiver (利用三态缓冲器实现数据双向传送),Bus Transceiver (总线收发 图656),Digital Logic Design and Application (数字逻辑设计及应用),27,6.7 Multiplexer（多路复用器）,Digital Switch, Multi-Switch, Data Selector (又称数据开关、多路开关、数据选择器) （缩写：MUX） Under Select Controlling Signals, Select One of the Multi-Inputs to the Output (在选择控制信号的作用下， 从多

17、个输入数据中选择其中一个作为输出。),Digital Logic Design and Application (数字逻辑设计及应用),28,28,Multiplexer (Mux),Mux: Another popular combinational building block Routes one of its N data inputs to its one output, based on binary value of select inputs,29,29,Multiplexer (Mux),4 input mux needs 2 select inputs to indicat

18、e which input to route through 8 input mux 3 select inputs N inputs log2(N) selects Like a rail yard switch,30,6.7 Multiplexer（多路复用器）,Enable 使能,Select 选择,数据输出（1位）,Digital Logic Design and Application (数字逻辑设计及应用),31,31,Mux Internal Design,2,1,i1,i0,s0,0,d,2,1,i1,i0,s0,d,0,i0 (1*i0=i0),i0 (0+i0=i0),2x

19、1 mux,0,32,32,Mux Internal Design,33,A B C,8-Input,1-bit Multiplexer,Digital Logic Design and Application (数字逻辑设计及应用),34,2-Input,4-bit Multiplexer,Digital Logic Design and Application (数字逻辑设计及应用),35,双4选1,A B,Truth Table for a 74x153 4-Input, 2-bit Multiplexer,36,Expanding Multiplexers(扩展多路复用器),Expan

20、ding Bit (扩展位) How to Realize 8-Input, 16-bit Multiplexer? (如何实现8输入，16位多路复用器？) From 8-Input, 1-bit to 8-Input, 16-bit (由8输入1位8输入16位) Need 16 74x151, Each Chip Process 1-bit (需要16片74x151， 每片处理输入输出中的1位),Digital Logic Design and Application (数字逻辑设计及应用),37,Expanding Multiplexers(扩展多路复用器),Expanding Bit (

21、扩展位) Select-Inputs Connect to C,B,A of Each Chip (选择端连接到每片的C,B,A) Note: The Fanout Ability of Select field (注意：选择端的扇出能力) （驱动16个负载）,Digital Logic Design and Application (数字逻辑设计及应用),38,Expanding Inputs (扩展数据输入端的数目) How to realize 32-Input, 1-bit Multiplexer (如何实现32输入，1位多路复用器？) Inputs from 8 to 32, Nee

22、d 4 chips ( 数据输入由832，需4片) How to control Select Inputs - By High bit plus Low bit. ( 如何控制选择输入端？ 分为：高位低位),Expanding Multiplexers(扩展多路复用器),39,Expanding Inputs (扩展数据输入端的数目) 如何实现32输入，1位多路复用器？ High Bits plus Decoder as Select ( 高位译码器进行片选) Low Bits Connect to C,B,A of each Chip ( 低位接到每片的C,B,A) Output Usin

23、g OR Gate ( 4片输出用或门得最终输出),Expanding Multiplexers(扩展多路复用器),Figure 6-60,40,Dual 4-to-1 Multiplexer to 8-to-1 Multiplexer (用双4选1数据选择器构成8选1数据选择器),41,41,Mux Example,City mayor can set four switches up or down, representing his/her vote on each of four proposals, numbered 0, 1, 2, 3 City manager can displ

24、ay any such vote on large green/red LED (light) by setting two switches to represent binary 0, 1, 2, or 3,42,Mux Example,Use 4x1 mux,43,43,Muxes Commonly Together N-bit Mux,Ex: Two 4-bit inputs A (a3 a2 a1 a0), and B (b3 b2 b1 b0) 4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can select between A or B,44,Muxes Commonly Together N-bit Mux,45,45,N-bit Mux Example,Four possible display items Temperature (T), Average miles-per-gallon (A) Instantaneous mpg (I), a