Apollo硬件设计原理图checklist.docx

Intel Pentium and Celeron Processor N- and J- Series (Formerly Apollo Lake)Schematics ChecklistJune 2017Revision 2.2Intel ConfidentialYou may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein.No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at .Intel technologies may require enabled hardware, specific software, or services activation. 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All rights reserved.Contents1Checklist Summary61.1References62General Information72.1Customer Implementation of Voltage Rails73Apollo Lake SoC83.1Platform Clock Signals83.1.1Crystal Component Selection Recommendation83.2RTC Circuitry103.3DDR3L Memory Interfaces113.3.1DDR3L SODIMM Memory Channel Interface113.3.2SODIMM VREF133.4LPDDR3 Memory Interfaces143.4.1LPDDR3 Memory Down Channel Interface143.4.2LPDDR3 Memory Down Reference and Compensation153.5Digital Display Interface-HDMI and DP163.5.1Digital Display Interface Supported163.5.2Digital Display Interface Signals Mapping163.5.3DDI Interface Connectivity173.5.4DDI Disable Guidelines203.5.5DisplayPort Dual Mode Support Protection Circuit213.6eDP223.6.1MIPI DSI Interface Native MIPI Panel223.7Camera Interface233.7.1MIPI CSI-2 InterfaceFour (x4) Lanes233.7.2Camera Side Band Signals243.8Storage Interfaces243.8.1SD Card Interface243.8.2eMMC* Interface253.8.3SATA 3.0 Port273.9PCIe Interface283.10LPE Audio I2S Interfaces293.11Serial I/O Interface313.11.1Fast Serial Peripheral Interface313.11.2LPSS SPI Interface313.11.3LPSS UART Signals323.12EC and PMU Interface Signals333.13SVID Interface Signals353.14Thermal Management and Miscellaneous Signals353.15GPIOs353.16Hardware Strap353.17Power Delivery and Decoupling Guidelines353.18Power Sequencing Checklist363.19Intel High Definition Audio (Intel HD Audio) Interface383.20SMBus Interface Signals393.21Platform Debug Port Design393.21.1MIPI-60 Connector Depopulation423.21.2Intel DCI Implementation433.22TXE Debug Hooks433.23EMI and ESD443.24Miscellaneous Signal443.25USB Interfaces453.25.1USB 2.0 Ports453.25.2USB 3.0 Ports463.25.3SSIC Ports463.25.4I2C Interface Signals473.26LPC Interface Signals483.27IISS Design Checklists483.27.1Sensors List49FiguresFigure 1. SoC 19.2 MHz Reference Clock Oscillator Circuits9Figure 2. External Circuitry for RTC11Figure 3. SODIMM VREF Generation Example Circuit13Figure 4. VREFDQ/VREFCA Connection16Figure 5. HDMI HPD Passgate Design Recommendation19Figure 6. HDMI DDC Cost Reduced Level Shifter Design Recommendation19Figure 7. USB_VBUSSNS Reference Circuit46 TablesTable 1. MIPI-60 Connector Pinout40Table 2. APL SoC JTAG Signals used on the MIPI-60 Connector42Table 3. Recommended Test Points when MIPI-60 Connector Removed43Table 4. Intel APS Connector43Table 5. ROM Bypass Strap Jumper43Table 6. Power Rails Checklist44Table 7. Ambient Light Sensor (ALS) Details (Sheet 1 of 2)49Table 8. Ambient Light Sensor (ALS) Details (Sheet 2 of 2)49Table 9. Gyroscope Details49Table 10. Magnetometer Details50Table 11. Accelerometer Details (Sheet 1 of 2)50Table 12. Accelerometer Details (Sheet 2 of 2)50Table 13. Pressure Sensor Details50Table 14. Optional Second Accelerometer (For 360 Degree Hinge Designs)51Table 15. Intel Sensor Solution BOM Checklist51Table 16. Sensors Debug Connector Checklist52Table 17. FW Debug Connector Checklist52Table 18. General Checklist52Table 19. Power Rails Checklist52Table 20. Apollo Lake Sensors Interrupt/GPIO Checklist53Revision HistoryDocument NumberRevision NumberDescriptionRevision Date5625571.0 Initial release.November 20155625571.2 Updated LPDDR3 Memory Down Channel Interface, PMU Power Management Signals, PROCHOT, SATA, PCIe, LPC, USB2.0, Debug, FAST SPI, LPSS SPI, Intel HD Audio, I2S, eDP, DDI, SD Card, UART sections. Added Power Sequencing Checklist. Removed SSIC port signal usage. March 20165625571.5 Updated USB2.0 section Updated SoC_PWROK and RSM_RST_N signal usageJune 20165625572.0 Updated eMMC section Updated USB2_OTG_ID to USB2_DUALROLE_IDJuly 20165625572.1 Updated eMMC section Updated Thermtrip notes Updated PCIe sectionJan 20175625572.2 Updated Platform Clock Signals Updated DDI/eDP Interface Connectivity Updated HDMI/eDP HPD Passgate Design Recommendation Updated DisplayPort Dual Mode Circuit Recommendation Updated SMBus Signals Updated Section: Platform Debug Port DesignJune 2017Schematics Checklist Intel Confidential 5Apollo Lake SoC1 Checklist SummaryThe following checklist provides design recommendations and guidance for the Apollo Lake platform. This document should not be used as a substitute for the Platform Design Guide.Note: Refer Apollo Lake Platform customer reference board files and rework guideline documents for more details.1.1 ReferencesDocumentDocument No./LocationApollo Lake SoC External Design Specification (EDS) Volume 1 of 4557555Apollo Lake Platform Design Guide557775 Apollo Lake Platform Customer Reference Board with DDR3L Technical Documentation Kit559031Apollo Lake Platform Customer Reference Board with LPDDR3 and TI* PMIC - Technical Documentation Kit560683Apollo Lake Platform Customer Reference Board with LPDDR3 and Richtek* PMIC - Technical Documentation Kit561386Apollo Lake Platform Customer Reference Board with LPDDR3 and Rohm* PMIC - Technical Documentation Kit561235Apollo Lake Platform Customer Reference Board - Rework Notes - User Guide5625362 General InformationThe following section for generic design information and configurations must be filled out by the customer or Intel field representative.Apollo Lake Platform InformationPMIC SolutionPart#/Vendor:Target ICC (max):Target Thermal Envelope (Watts)Form FactorPanel Vendor and SizePart#/Vendor:LED Backlight SupplyPart#/Vendor:3G SolutionPart#/Vendor:Wi-Fi solutionOther Wireless Solutions (BT, GNSS, NFC and so on.)Platform SensorsBattery life/Battery Pack FormatTarget:Target FCS (First Customer Ship) Date2.1 Customer Implementation of Voltage RailsFill in the schematic name of voltage rails and mark boxes when rails are powered on.Power Rail NamePower StatusNotesS0S0ixSoC G3/RTC3 Apollo Lake SoC3.1 Platform Clock SignalsPin NameSystemPull-up/Pull-downSeries TerminationNotesOSCINOSCOUTN/AN/AConnect to a 19.2MHz crystal. Parallel resistor (200K) across crystal and capacitor from every pin to GND, the value of capacitor is dependent on crystal vendor recommendations. For crystal components selection, refer PDG.PCIE_REF_CLK_RCOMP60.4 (1%) PD to GND.N/AThis resistor should be placed as close to SoC as possible.PMU_SUSCLKN/AN/AConnect from SoC for 32K clock output.PCIE_CLKOUT_3:0P PCIE_CLKOUT_3:0NPCI Express* Clock Output: Serial Reference 100- MHz PCIe* 3.0 specification compliant differential output clocks to PCIe* devices.OSC_CLK_OUT_ 2:0Platform Clock: clock output programmable in the range of 6.75-26 MHz. Usage: for Camera.OSC_CLK_OUT_3Platform Clock: clock output at 19.2MHz only. Usage: NFC. NOTES:1. For SUSCLK feature, the PMU SUSCLK SoC pin can be used on the platform with a clock buffer to provide Wi-Fi or EC 32K clock outputs or GPIO_31-33Refer EDS to select Function 5 for these GPIOs can be used to provide 32K clock outputs to WWAN/GPS.2. PCIE CLKOUT or PCIEREFCLK can be used to provide 100MHz output clocks to 4 PCIe devices.3. Refer PDG and CRB for RC filter recommendations for OSC_CLK_OUT3:0 signals.3.1.1 Crystal Component Selection RecommendationThe SoC reference clock oscillator consists of an on-die pierce oscillator, coupled with a few external components, including two capacitors and a crystal, as shown in the figure below.Figure 1. SoC 19.2 MHz Reference Clock Oscillator CircuitsNOTES:1. Crystal X1, Resistor Rf and capacitors C1 and C2 are on the board. Traces labeled OSCOUT and OSCIN connect the on-die to the on-board circuitry.2. OSCOUT and OSCIN should be shielded by VSS.3. Frequency tolerance and stability = 30 ppm.4. Rf=200 K, Rs1=Rs2=0 , C1=C2=18 pF (+/-5%)(with assumption that crystal load capacitance = 12pF)5. Rs1=Rs2=0 is optional and can be replaced with trace. This is for debug purpose. 6. Refer PDG for details. CapacitorsThe external capacitive load to be used with the crystal must account for pin and trace capacitances. In selecting the value for the external load capacitors (C1 and C2), use the following formula:C1 = C2 = 2 * CL (Cs + Ci), Where: C1 = C2 = External Load Capacitor Value (discrete components on the board) CL = Specified Crystal Capacitive Load (found in the crystal data sheet) Cs = Board Trace Capacitance (includes crystal pad capacitance) (2-10 pF) Ci = SoC Pin Capacitance (2-3 pF)Due to vendor variation in crystal characteristics, layout variations and PCB trace capacitance differences, the above calculation should be performed for each design to determine the precise value of C1 and C2 that is optimal for the particular platform. Also note that if an existing design did not follow the ICLK_OSCIN and ICLK_OSCOUT trace separation guidelines, there may be an additional parasitic capacitance that appears across the crystal, requiring further decreases in the value of C1 and C2. These should be calculated for such designs and factored into component selection. Future board revisions should incorporate the recommended layout guidelines. CrystalThe SoC low power oscillator design requires a high Q crystal to filter out noise and increase signal amplitude. Q is easily calculated from the crystal manufacturers datasheet, using the following formula:1/ (2*pi*Freq*R*C)In this formula, R and C are the series resistance and capacitance of the crystal model, which is obtained from the vendor or listed in the data sheet. Frequency is 19.2 MHz (1.92 * 107Hz).3.2 RTC CircuitryPin NameSystemPull-up/Pull-down NotesRTC_X1RTC_X2N/AConnect a 32.768- kHz crystal oscillator across these pins with a 10- MW resistor and a decoupling cap at each signal. Values for C1 and C2 are dependent on crystal are required to maintain the accuracy of the RTC. Note: The external circuitry shown in Figure 2. External Circuitry for RTC. RSM_RST_N20k PU(as needed, if EC output is open drain) and PD 100K to GND.RTC ResetResume RTC Well ResetRTC_RST_NRefer PDG.Secondary RTC Reset: This signal resets the manageability register bits in the RTC well when the RTC battery is removed. Note: The RTC_RST_N input must always be high when all other RTC power planes are on.RTC_TEST_NRefer PDG.An RC delay circuit with a time delay in the range of 18ms to 25ms should be provided. The recommended values for resistor and capacitor are 20 k and 1.0F. The circuit should be connected to RTC_VCC (+VCCRTC_3P3).RTC Battery TestBad Battery detect. This signal is asserted when a bad battery is detected (discharge below 2V)INTRUDER_NIntruder Detect Note: This pin cannot be used as a GPIO.The INTRUDER_N signal can be used to disable system if box detected open. When not used, this signal shall be pulled high with 47K-330k Ohm resistor to RTC rail. A floating INTRUDER_N pin can cause higher RTC power well leakage.VCC_RTC_EXTPAD0.1 F10% connect to GNDFigure 2. External Circuitry for RTC NOTES:1. The exact capacitor values for C1 and C2 must be based on the crystal maker recommendations. Typical values for C1 and C2 are 18 pF, based on crystal load of 12.5 pF. This is an example value for the mentioned C1, C2 and crystal load.2. Reference designators are arbitrarily assigned.3. VCC_3P3V_A is active whenever the system is plugged in. 4. Vbatt is voltage provided by the battery.5. RTC_VCC, RTC_X1, and RTC_X2 are SoC pins. 6. RTC_VCC powers the SoC RTC well.7. RTC_X1 is the input to the internal oscillator.8. RTC_X2 is the feedback for the external crystal.3.3 DDR3L Memory Interfaces3.3.1 DDR3L SODIMM Memory Channel InterfacePin NameSystem Pull-up/Pull-down Schematic NotesMEM_CH0_DQ 63:0MEM_CH1_DQ 63:0N/ATo respective DQ# on SODIMM.MEM_CH0_DQS 7:0_PMEM_CH0_DQS 7:0_NMEM_CH1_DQS 7:0_PMEM_CH1_DQS 7:0_NN/ATo respective DQS# on SODIMM.MEM_CH0_MA15:0MEM_CH1_MA15:0N/AMA0.15 in sequence To SODIMM 98, 97, 96,95,92, 91,90, 86, 89,85,107, 84,83, 119, 80,78)MEM_CH0_BA2:0MEM_CH1_BA2:0N/ATo SODIMM BA (BS0=Pin 109, BS1=108,BS2= 79)MEM_CH0_RAS_NMEM_CH1_RAS_NN/ATo SODIMM RAS (pin 110).MEM_CH0_CAS_NMEM_CH1_CAS_NN/ATo SODIMM CAS (pin 115).MEM_CH0_WE_NMEM_CH1_WE_NN/ATo SODIMM WE (pin 113).MEM_CH0_CS1,0_NMEM_CH1_CS1,0_NN/ATo SODIMM CS (SODIMM pin 114 =CS#0 / pin 121 =CS#1).MEM_CH0_CKE1,0MEM_CH1_CKE1,0N/ATo SODIMM CKE# (SODIM pin 73 = CKE#0/ pin 74= CKE#1).MEM_CH0_ODT1,0MEM_CH1_ODT1,0N/ATo SODIMM ODT0/1 (pin 116 =ODT 0/ pin 120 =ODT 1).MEM_CH0_CK1,0_PMEM_CH1_CK1,0_PN/ATo SODIMM CKP (pin 101 =CKP0 / 102 = CKP1).MEM_CH0_CK1,0_NMEM_CH1_CK1,0_NN/ATo SODIMM CKP (pin 103 = CKN0 / 104 =CKN1).Pin Name /DescriptionSchematic NotesMEM_CH0_RCOMPMEM_CH1_RCOMP105 (1%) PD to GND.All RCOMP resistors have 1% tolerance(This resistor should be placed as close to SoC as possible.)MEM_CH0_VREFCAMEM_CH0_VREFDQMEM_CH1_VREFCAMEM_CH1_VREFDQRefer Figure belowMEM_CH0_RESET_NMEM_CH1_RESET_NDirect connection to RST# on SODIMM slot. A 1k pull up to VDDQ is required.NOTE: It is preferred to route the reset signal in Dual Stripline. Incase of Microstrip routing, it is recommended to add a placeholder for a series RC filterR=0ohms, C=0.1uF(unstuff) located within 350 mils from the reset pin to address ESD concerns.SODIMM decouplingRefer APL PDG Chapter 5: Memory.3.3.2 SODIMM VREFFigure 3. SODIMM VREF Generation Example CircuitNOTE: APL SoC VREF outputs can be left No Connect for DDR3L SODIMM.3.4 LPDDR3 Memory Interfaces3.4.1 LPDDR3 Memory Down Channel InterfacePin NameSystem Pull-up/Pull-down Schematic NotesMEM_CH0_DQ31:0_AMEM_CH0_DQ 31:0_BMEM_CH1_DQ31:0_AMEM_CH1_DQ 31:0_BConnect to DRAM A/B of DQ 31:0 pins of memory down devices.MEM_CH0_DQS3:0_P_AMEM_CH0_DQS3:0_P_BMEM_CH1_DQS3:0_P_AMEM_CH1_DQS3:0_P_BConnect to DRAM A/B of DQS 3:0_T pins of memory down devices.MEM_CH0_DQS3:0_N_AMEM_CH0_DQS3:0_N_BMEM_CH1_DQS3:0_N_AMEM_CH1_DQS3:0_N_BConnect to DRAM A/B of DQS 3:0C pins of memory down devices.MEM_CH0_DQ15:0_A/BMEM_CH0_DQS1:0_P_A/BMEM_CH0_DQS1:0_N_A/BMEM_CH1_DQ15:0_A/BMEM_CH1_DQS1:0_P_A/BMEM_CH1_DQS1:0_N_A/BConnect to DQ15:0, DQS1:0_T, and DQS1:0_C of LPDDR3 DRAM device (Mandatory)Note: For LPDDR3, limited to 4 (four) bytes of each x32 channel Note: For LPDDR3, the BIOS will need to include the swap informationNote: CH0_A has 4 bytes. Can swap among these 4 bytes. CH0_B has 4 bytes .Can swap among these 4 bytes. You cannot swap bytes between CH0_A and CH0_B.MEM_CH0_CAA9:0MEM_CH0_CAB9:0MEM_CH1_CAA9:0MEM_CH1_CAB9:0Connect to CA9:0 pins of memory down devices (A and B)Refer PDG for termination detailsMEM_CH0_CLK0_P_AMEM_CH0_CLK0_P_BMEM_CH0_CLK1_N_AMEM_CH0_CLK1_N_BMEM_CH1_CLK0_P_AMEM_CH1_CLK0_P_BMEM_CH1_CLK1_N_AMEM_CH1_CLK1_N_BConnect differential termination between CK_T_A/B and CK_C_A/B. Value is 75 ohmsMEM_CH0_CS1:0A_NMEM_CH0