ALU的VHDL设计.doc

- TOPLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_SIGNED.ALL;ENTITY ALU ISPORT(AIN1,AIN2,AIN3,AIN4,BIN1,BIN2,BIN3,BIN4,CZ,DIN1,DIN2 : IN STD_LOGIC;SUMM1,SUMM2,SUMM3,SUMM4,CO : OUT STD_LOGIC);END ENTITY ALU;ARCHITECTURE BEHAV7 OF ALU ISCOMPONENT summary1 PORT( A1,A2,A3,A4,B1,B2,B3,B4,C1,K1 : IN STD_LOGIC; SUM1,SUM2,SUM3,SUM4,COUT1 : OUT STD_LOGIC);END COMPONENT;COMPONENT summary2PORT( A1,A2,A3,A4,C2,K2 : IN STD_LOGIC; SUM1,SUM2,SUM3,SUM4,COUT2: OUT STD_LOGIC);END COMPONENT;COMPONENT logic1PORT( A1,A2,A3,A4,B1,B2,B3,B4,C3,K3 : IN STD_LOGIC; SUM1,SUM2,SUM3,SUM4 : OUT STD_LOGIC);END COMPONENT;COMPONENT logic2PORT( A1,A2,A3,A4,B1,B2,B3,B4,C4,K4 : IN STD_LOGIC; SUM1,SUM2,SUM3,SUM4 : OUT STD_LOGIC);END COMPONENT;COMPONENT LogicCtrlPORT( D1,D2 : IN STD_LOGIC; K11,K22,K33,K44 : OUT STD_LOGIC);END COMPONENT;COMPONENT or4aPORT( p1,q1,r1,s1 : IN STD_LOGIC; t1 : OUT STD_LOGIC);END COMPONENT;COMPONENT or4bPORT( p2,q2,r2,s2 : IN STD_LOGIC; t2 : OUT STD_LOGIC);END COMPONENT;COMPONENT or4cPORT( p3,q3,r3,s3 : IN STD_LOGIC; t3 : OUT STD_LOGIC);END COMPONENT;COMPONENT or4dPORT( p4,q4,r4,s4 : IN STD_LOGIC; t4 : OUT STD_LOGIC);END COMPONENT;COMPONENT or2aPORT( j,k : IN STD_LOGIC; l : OUT STD_LOGIC);END COMPONENT;SIGNAL W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14, W15,W16,W17,W18,W19,W20,W21,W22 : STD_LOGIC; BEGINU1 : LogicCtrl PORT MAP (D1 = DIN1, D2 = DIN2, K11 = W1, K22 = W2, K33 = W3, K44 = W4);U2 : summary1 PORT MAP ( A1 = AIN1, A2 = AIN2, A3 = AIN3, A4 = AIN4, B1 = BIN1, B2 = BIN2,B3 = BIN3, B4 = BIN4, C1 = CZ, K1 = W1, SUM1 = W5, SUM2 = W6, SUM3 = W7, SUM4 = W8, COUT1 = W9);U3 : summary2 PORT MAP (A1 = AIN1, A2 = AIN2, A3 = AIN3, A4 = AIN4, C2 = CZ, K2 = W2,SUM1 = W10, SUM2 = W11, SUM3 = W12, SUM4 = W13, COUT2 = W14);U4 : logic1 PORT MAP (A1 = AIN1, A2 = AIN2, A3 = AIN3, A4 = AIN4, B1 = BIN1, B2 = BIN2, B3 = BIN3, B4 = BIN4, C3 = CZ, K3 = W3, SUM1 = W15, SUM2 = W16, SUM3 = W17, SUM4 = W18);U5 : logic2 PORT MAP (A1 = AIN1, A2 = AIN2, A3 = AIN3, A4 = AIN4, B1 = BIN1, B2 = BIN2, B3 = BIN3, B4 = BIN4, C4 = CZ, K4 = W4, SUM1 = W19, SUM2 = W20, SUM3 = W21, SUM4 = W22); U6 : or2a PORT MAP (j = W9, k = W14, l = CO);U7 : or4a PORT MAP (p1 = W5, q1 = W10, r1 = W15, s1 = W19, t1 = SUMM1);U8 : or4b PORT MAP (p2 = W6, q2 = W11, r2 = W16, s2 = W20, t2 = SUMM2);U9 : or4c PORT MAP (p3 = W7, q3 = W12, r3 = W17, s3 = W21, t3 = SUMM3);U10 : or4d PORT MAP (p4 = W8, q4 = W13, r4 = W18, s4 = W22, t4 = SUMM4);END ARCHITECTURE BEHAV7;-4位数的与和或的实现LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY logic1 ISPORT( A1,A2,A3,A4,B1,B2,B3,B4,C3,K3 : IN STD_LOGIC; SUM1,SUM2,SUM3,SUM4 : OUT STD_LOGIC);END ENTITY logic1;ARCHITECTURE BEHAV4 OF logic1 ISSIGNAL d11,d12,d13,d14,d1o,d21,d22,d23,d24,d2o,d31,d32,d33,d34,d3o,d41,d42,d43,d44,d4o : STD_LOGIC;BEGINPROCESS(A1,A2,A3,A4,B1,B2,B3,B4,C3,K3)BEGINd11 = (A1 AND B1) AND C3;d12 = (NOT A1) AND B1) AND C3;d13 = (A1 AND (NOT B1) AND C3;d14 = (A1 AND B1) AND (NOT C3);d1o = (d11 OR d12) OR d13) OR d14;-d21 = (A2 AND B2) AND C3;d22 = (NOT A2) AND B2) AND C3;d23 = (A2 AND (NOT B2) AND C3;d24 = (A2 AND B2) AND (NOT C3);d2o = (d21 OR d22) OR d23) OR d24;-d31 = (A3 AND B3) AND C3;d32 = (NOT A3) AND B3) AND C3;d33 = (A3 AND (NOT B3) AND C3;d34 = (A3 AND B3) AND (NOT C3);d3o = (d31 OR d32) OR d33) OR d34;-d41 = (A4 AND B4) AND C3;d42 = (NOT A4) AND B4) AND C3;d43 = (A4 AND (NOT B4) AND C3;d44 = (A4 AND B4) AND (NOT C3);d4o = (d41 OR d42) OR d43) OR d44;-SUM1 = d1o AND K3;SUM2 = d2o AND K3;SUM3 = d3o AND K3;SUM4 = d4o AND K3;END PROCESS;END ARCHITECTURE BEHAV4;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY logic2 ISPORT( A1,A2,A3,A4,B1,B2,B3,B4,C4,K4 : IN STD_LOGIC; SUM1,SUM2,SUM3,SUM4 : OUT STD_LOGIC);END ENTITY logic2;ARCHITECTURE BEHAV5 OF logic2 IS BEGINPROCESS(A1,A2,A3,A4,B1,B2,B3,B4,C4,K4)BEGINSUM1 = (A1 XOR (NOT B1) NAND C4) AND K4;SUM2 = (A2 XOR (NOT B2) NAND C4) AND K4;SUM3 = (A3 XOR (NOT B3) NAND C4) AND K4;SUM4 = (A4 XOR (NOT B4) NAND C4) AND K4;END PROCESS; END ARCHITECTURE BEHAV5;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY LogicCtrl ISPORT( D1,D2 : IN STD_LOGIC; K11,K22,K33,K44 : OUT STD_LOGIC);END ENTITY LogicCtrl;ARCHITECTURE BEHAV6 OF LogicCtrl IS BEGINPROCESS(D1,D2)BEGINK11 = (NOT D2) AND (NOT D1);K22 = (NOT D2) AND D1;K33 = D2 AND (NOT D1);K44 = D1 AND D2;END PROCESS; END ARCHITECTURE BEHAV6;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY or2a ISPORT( j,k : IN STD_LOGIC; l : OUT STD_LOGIC);END ENTITY or2a;ARCHITECTURE one OF or2aISBEGINl = j OR k;END ARCHITECTURE one;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY or4d ISPORT( p4,q4,r4,s4 : IN STD_LOGIC; t4 : OUT STD_LOGIC);END ENTITY or4d;ARCHITECTURE ONE OF or4d ISBEGINt4 = (p4 OR q4) OR (r4 OR s4);END ARCHITECTURE ONE;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY summary1 IS PORT( A1,A2,A3,A4,B1,B2,B3,B4,C1,K1 : IN STD_LOGIC; SUM1,SUM2,SUM3,SUM4,COUT1 : OUT STD_LOGIC);END ENTITY summary1;ARCHITECTURE BEHAV1 OF summary1 IS BEGINPROCESS(A1,A2,A3,A4,B1,B2,B3,B4,C1,K1)BEGINSUM1 = (A1 XOR (B1 XOR C1)XOR C1) AND K1;SUM2 = (A2 XOR (B2 XOR C1)XOR (A1 AND (B1 XOR C1)OR(A1 OR (B1 XOR C1)AND C1) AND K1;SUM3 = (A3 XOR (B3 XOR C1) XOR (A2 AND (B2 XOR C1)OR(A2 OR (B2 XOR C1)AND A1 AND (B1 XOR C1)OR (A2 OR (B2 XOR C1)AND(A1 OR (B1 XOR C1)AND C1) AND K1;SUM4 = (A4 XOR (B4 XOR C1) XOR (A3 AND (B3 XOR C1)OR(A3 OR (B3 XOR C1)AND A2 AND (B2 XOR C1)OR(A3 OR (B3 XOR C1)AND(A2 OR (B2 XOR C1)AND A1 AND (B1 XOR C1) OR(A3 OR (B3 XOR C1)AND(A2 OR (B2 XOR C1)AND(A1 OR (B1 XOR C1)AND C1) AND K1;COUT1 = (A4 XOR (B4 XOR C1)AND(A3 XOR (B3 XOR C1)AND(A2 XOR (B2 XOR C1)AND(A1 XOR (B1 XOR C1)AND C1) OR(A4 XOR (B4 XOR C1)AND(A3 XOR (B3 XOR C1)AND(A2 XOR (B2 XOR C1)AND A1 AND (B1 XOR C1) OR(A4 XOR (B4 XOR C1)AND(A3 XOR (B3 XOR C1)AND A2 AND (B2 XOR C1) OR (A4 XOR (B4 XOR C1)AND A3 AND (B3 XOR C1) OR (A4 AND (B4 XOR C1) XOR C1) AND K1;END PROCESS;END ARCHITECTURE BEHAV1;LIBRARY IE