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毕业设计
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4位CMOS流水线ADC的设计,毕业设计
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008 787A 0.5-V 8-bit 10-Ms/s Pipelined ADCin 90-nm CMOSJunhua Shen and Peter R. Kinget, Senior Member, IEEEAbstractThis paper presents a pipelined analog-to-digitalconverter (ADC) operating from a 0.5-V supply voltage. The ADCuses true low-voltage design techniques that do not require anyon-chip supply or clock voltage boosting. The switch OFF leakagein the sampling circuit is suppressed using a cascaded samplingtechnique. A front-end signal-path sample-and-hold amplifier(SHA) is avoided by using a coarse auxiliary sample and hold(S/H) for the sub-ADC and by synchronizing the sub-ADC andpipeline-stage sampling circuit. A 0.5-V operational transcon-ductance amplifier (OTA) is presented that provides inter-stageamplification with an 8-bit performance for the pipelined ADCoperating at 10 Ms/s. The chip was fabricated on a standard90 nm CMOS technology and measures 1.2 mm 1.2 mm. Theprototype chip has eight identical stages and stage scaling wasnot used. It consumes 2.4 mW for 10-Ms/s operation. Measuredpeak SNDR is 48.1 dB and peak SFDR is 57.2 dB for a full-scalesinusoidal input. Maximal integral nonlinearity and differentialnonlinearity are 1.19 and 0.55 LSB, respectively.Index TermsAnalog-to-digital converter (ADC), cascadedsampling, low-voltage operational transconductance amplifier(OTA), pipelined ADC, switch leakage, ultra-low-voltage analogcircuits.I. INTRODUCTIONTHE research goal of exploring ultra-low-voltage analogcircuit design is motivated by several trends in integratedcircuit design and semiconductor technologies and the applica-tions they enable. System-on-a-chip (SOC) designs have madepossible substantial cost and form factor reductions, in partsince they integrate crucial analog interface circuits, such asanalog-to-digital converters (ADCs), with digital computingand signal processing circuits on the same die. The interfacesonly occupy a small fraction of the chip die and, for SOCdesigns, the technology selection and system design choicesare mainly driven by digital circuit requirements. In the pastdecades, design techniques for analog interface circuits thatare fully compatible with scaled standard digital CMOS tech-nologies and do not require special technology options havebeen important enablers to continue ever more complex SOCdesigns (see, e.g., 1). As the feature sizes in modern nanoscaleCMOS technologies reduce, the maximum supply voltage alsohas to be reduced to maintain reliable device operation. TheInternational Technology Roadmap for Semiconductors (ITRS)foresees that the supply voltage for low-power digital circuitswill scale below 1 V for high-performance applications andManuscript received August 27, 2007; revised October 22, 2007. This workwassupportedbyRealtekCorporation.Chipprototypefabricationwasprovidedby United Microelectronics Corporation.The authors are with the Department of Electrical Engineering, ColumbiaUniversity, New York, NY 10027 USA (e-mail: kinget).Digital Object Identifier 10.1109/JSSC.2008.917470down to 0.5 V for low-power applications within the nextdecade or so 2. Additionally, the most energy-efficient opera-tion of digital systems occurs for supply voltages between 0.3and 0.5 V in deeply scaled technologies.Scavenging the energy to operate circuits from the environ-ment is desirable for applications such as wireless sensor nodesor ambient intelligence. e.g., if, due to space constraints, onlyone solar cell is available, the supply voltage is about 0.5 V 3,4.Pipelined ADCs are a popular choice for analog-to-digitalconversion because of their attractive features of high opera-tion speed, good resolution, and low power consumption. In thisstudy, an 8-bit 10-Ms/s pipelined ADC is targeted with an ag-gressive low supply voltage of 0.5 V 5. In prior work, severaltechniques have been developed to accommodate low-voltageanalog circuit design such as the use of special low- devices6, 7, on-chip clock and gate voltage boosting 811, bodydriven circuits 12, 13, or switched-opamp 1416 tech-niques. Low- devices require extra masks during fabrica-tion and thus result in higher cost. On-chip voltage boosting canlead to long-term reliability concerns, especially for nanoscaleCMOS devices. Using the body terminal of a MOSFET offersthe circuit designer a number of interesting circuit design op-portunities, but the body transconductance is significantlysmaller than the gate transconductance , which can limit theattainable speed or noise performance. Switched-opamp tech-niqueshavebeensuccessfullyusedforverylow-voltagedesignsbuttypically operate at a reduced operation frequency due to theamplifier turn-on times.The work presented here is using true low-voltage designtechniques to take full advantage of advanced CMOS technolo-gies without resorting to special devices or on-chip voltageboosting. In Section II, the top-level design of the pipelinedADC is presented and the use of an auxiliary sample andhold for the sub-ADC is introduced. Cascaded sampling asa solution to address switch-off-state leakage is discussed inSection III. Section IV discusses the design of the 0.5-V opera-tional transconductance amplifier (OTA). Experimental resultsare presented in Section V, followed by concluding remarks inSection VI.II. LOW-VOLTAGE PIPELINED ADC DESIGNA. Top-Level and Stage Design ConsiderationsIn ultra-low-voltage analog design, one intrinsic challenge isthe reduced available signal swing. It makes multi-bit stagesnot desirable due to comparator offset and hysteresis concerns.0018-9200/$25.00 2008 IEEEnts788 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008Fig. 1. (a) Block diagram of the pipeline ADC prototype chip and (b) single-ended version of one pipeline stage. (c) Nonoverlapping clock signals 4030 5930 41 andtheir advanced 4030 5930 41 and delayed versions used to minimize charge injection and clock feedthrough and to ensure accurate sampling.Multi-bit stages further require a higher open-loop gainband-width (GBW) for the residue amplifiers due to the small feed-back factors in the stage. In this design, we use the 1.5-bit/stage architecture. Fig. 1(a) shows the block diagram of theconverter chip prototype. To simplify the prototype design, thesecond through the eighth stages were kept identical to the firststage, which has the most stringent performance requirements.In a redesign, the power consumption can be reduced by ap-plying progressive size and power scaling to the later stages. Nosample-and-holdamplifier (SHA)is implementedinfrontof thepipelined ADC to save power and reduce noise. This is madepossible by the introduction of an auxiliary sample and hold(S/H)for thesub-ADC,whichwill be presentedlaterinthissec-tion. A single-ended diagram of a stage of the pipelined ADC isshowninFig.1(b)forclarity,buttheactualchipimplementationis fully differential. It consists of two comparators as sub-ADCand a multiplying digital-to-analog converter (MDAC) that per-formssignalsampling,subtraction,andresidueamplification.A400-mV peak-to-peak differential full-scale input swing is tar-geted,takingintoaccountthetypicalavailableoutputswingofa0.5-V OTA. The signal common-mode voltage is set to 250 mVand the reference voltages are 250 mV 100 mV. For an 8 bitaccuracy level, the LSB of the ADC is still as large as 1.6 mV.The choice of the size of the sampling capacitor is driven bythe concern of keeping parasitic capacitors sufficiently small.To avoid an extra mask to realize the metalinsulatormetal(MIM) capacitors, an interdigitated metal1-through-metal6capacitor with a unit size of 250 fF and an area of 130 m wascustom designed and verified using electromagnetic simula-tions. In this design, four unit capacitors in a common-centroidlayout for improved matching are used to realize the sam-pling capacitors and . The RMS value of the thermalnoise for a 1 pF sampling capacitoris 64 and sufficiently small compared with one LSBvalue.The on-chip clock generator generates two nonoverlappingclock signals and from an external clock reference. Eachclock signal also has an advanced version and delayedntsSHEN AND KINGET: A 0.5-V 8-BIT 10-Ms/s PIPELINED ADC IN 90-nm CMOS 789Fig. 2. (a) Block diagram of the first stage of a conventional pipeline ADC with a dedicated front-end S/H and preamplifier (A) in the sub-ADC and (b) theassociated operation sequence. (c) Block diagram of the proposed pipeline stage with auxiliary S/H circuit and (d) its operation sequence.version , which are used to minimize charge injection andclock feedthrough and ensure accurate sampling, as shown inFig. 1(c). At the top level, the stages receive clock signals inreverse order, so that the clock signal edges advance slightlyalong the pipeline stages. This ensures that a succeeding stagealways samples the correct residue signal from the precedingstage.B. Auxiliary S/H for Sub-ADC PathThe conventional circuit architecture for the first stage of apipeline ADC includes a dedicated front-end SHA, as shown inFig. 2(a), to guarantee that the MDAC path and the sub-ADCpath operate on the same sample of the input signal. As shownin Fig. 2(b), the sub-ADC decides while the MDAC is samplingand the sub-ADC outputs are ready when the MDAC starts am-plifying. Additionally, preamplifiers are typically used in thecomparators of the sub-ADC to block their kickback noise 17.These approaches allow a fast operation of the ADC, but atthe cost of a dedicated front-end SHA circuit and comparatorpreamplifiers.Design techniques for signal path SHAs at ultra-low voltageshave been explored in 18. In this study, we propose an archi-tectural change to avoid the front-end SHA, as well as the com-parator preamplifiers. As shown in Fig. 2(c), a simple coarseauxiliary S/H is inserted into the sub-ADC path instead. ThisauxiliaryS/HsamplestheinputsignalduringthesamesamplingphaseastheMDACpath.Itholdstheinputsignalwhilethecom-parators in the sub-ADC make their decision at the start of theMDACs residue amplification phase see Fig. 2(d). The auxil-iary sampling clock and the comparison clock are nonoverlap-ping, so that the sampling switch is open during the comparatoroperation and the comparator regeneration and reset kickbacknoise are blocked from entering the signal path. In the presented10-Ms/s pipelined ADC design, the latched comparators, usingthe topology presented in 19, reach their decision in less than2% of the sampling clock period, which leaves plenty of timefor the MDAC to amplify the residue.1The auxiliary S/H can besignificantlyless accurate thana front-end SHA, sincesamplingerrors are equivalent to comparator offset and a 1.5 bit/stagepipelined ADC is very robust against such offsets.A mismatch between the time constants of the sampling net-work in the MDAC path and sub-ADC path translates into anoffset in the sub-ADC path 20, 21. Assuming that the sam-pling clock skew between these two paths can be neglected, theworst case mismatch error is 20(1)where is the full-scale single-ended input-signal amplitudeand is the maximum signal frequency. is defined as thesampling time constant or propagation delay(2)whereRCisthetimeconstantofthesamplingnetwork;sincethesampling network bandwidth is designed to be muchhigher than maximum input frequency , the approximationin (2) holds. In the presented ADC, is equal to , whichis 100 mV, and the 1.5 bit sub-ADC can tolerate an offset up1To further improve the design, the nonoverlapping time between the sam-pling and amplifying phase of the MDAC could be used to get the comparatoroutputs ready earlier.nts790 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008to , or 25 mV, so that, for a maximum signal frequencyof 5 MHz when sampling at 10 Ms/s, we obtain the followingrequirement:(3)This derivation assumes there are no other offsets in thesub-ADC path. If we allocate half of the total tolerable offsetto the comparators, the system is still able to tolerate a sam-pling-network time-constant difference between the MDACand sub-ADC of up to 4 ns.In the presented design, the RC network in the MDAC has atime constantsmaller than4ns to guaranteethe dynamic perfor-mance in the presence of nonlinear resistance of the switch, sothat, theoretically, the auxiliary S/H could be eliminated. How-ever, it is still used to block the comparator kickback noise andto allow for larger comparator offsets. The auxiliary S/H is re-alized with the same sampling switch as the MDAC path but asampling capacitor of about half the size. This sampling capac-itor is still large enough so that the channel charge injection andthe clock feedthrough from the switch do not affect the sampledvoltage significantly.III. CASCADED SAMPLING TO COMBAT OFF-SWITCHLEAKAGE IN NANOSCALE CMOSIn nanoscale CMOS technologies, subthreshold MOSleakage, MOS gate leakage, and reverse-biased PN junctionband-to-band tunneling become more and more significant2224. At an ultra-low supply voltage of 0.5 V, MOSgate leakage is substantially reduced since it is exponentiallydependent on the gate voltage. The reverse-biased PN junctionleakage becomes significant when the reverse biasing voltageexceeds the bandgap voltage, which does not occur with a0.5-V supply. The main leakage concern in this design is thesubthreshold leakage of switches in their OFF state, particularlyduring the nonoverlapping time between sampling and holdingphases, when a capacitor is not connected to any voltagesource. This leakage causes signal-dependent distortion in theswitched-capacitor S/H circuits.To illustrate the effect of this leakage, a basic S/H circuit andthe associated waveforms are shown in Fig. 3(a) and (b). Dueto the subthreshold switch leakage, the output voltage isnot held constant when is OFF. In the worst case, assuminga rail-to-rail signal at Nyquist rate, changes from V to 0after turns off; this puts in weak inversion and saturation.The leakage current increases exponentially for a decreasingthreshold voltage . Similar leakage challenges exist in eachstage of thepipelined ADC when theS/H switches are OFF.Thisissue is most severe in the first stage where noise and distortionshould be kept well below one LSB of the full ADC.To overcome this problem, a cascaded sampling technique isproposed to alleviate the switch subthreshold OFF leakage. Anextra switch and an additional smaller hold capacitor areused in front of the main switch and capacitor , as shownin Fig. 3(c). Switches and operate during the same clockphase, but is turned off slightly later to ensure that it doesnot affect the accurate sampling on . An intermediate voltageis now introduced which is held by the extra capacitor .During the track phase, both switches and are ON, andand track . In the hold phase, and are OFFand enter weak inversion. The difference between andis very small but slowly grows during the hold phase due tothe leakage of see Fig. 3(d). operates in weak inversionbut in the linear region with a very small drain-source voltage; the channel leakage current of each one of the transistorin is then(4)where is the aspect ratio of the transistor, is thethermal voltage, is the slope factor, and is transistorthreshold voltage. Since remains very small, the OFFcurrent in is very small and is kept close to constantduring the hold phase. The simulation results in Fig. 3(e) showthat the slope of the output voltage for the cascaded S/H isabout one tenth of the slope for the conventional one. In theworst case leakage scenario, when the transistors are in thefastfast process corner and operate at a temperature of 85 C,the proposed sampling circuit still has a leakage rate that is fourtimes lower.Since there are now two switches in series, the switch sizeneeds to be increased. The extra sampling capacitor can bekept much smaller than sampling capacitor to limit the areaoverhead and settling time impact. was set to or250fFinthisdesign.Theleakagecausedbythepathconnectingto during the nonoverlap period, does not introduce dis-tortion since the reference voltages are constant.Switch nonidealities result in important error contribu-tions including settling errors, charge-injection errors, andclock-feedthrough errors. The fully differential circuit topologylargely eliminates the latter two, but the voltage-dependentgate capacitance causes slightly different errors in the twodifferential paths. A switch design using a CMOS transmissiongate with half-sized dummy switches was adopted to largelysuppress clock feedthrough and charge injection. To reduce theswitch threshold voltage and improve settling during the ONstate, the switch-transistor gate and body terminals are shortedand connected to the clock signal 18. With a supply of only0.5 V, latch-up due to the forward-biased body junction is not aconcern 25.IV. 0.5-V OTA DESIGNThe residue amplifier is the most important active block ina pipelined ADC design. To achieve 8-bit resolution, the OTADC gain in the first pipeline stage should exceed 50 dB. As-suming a feedback factor of 1/3, which takes into account theinput parasitic capacitance of the OTA, the GBW should be atleast 18 MHz to achieve a settling accuracy better than 0.4 %for a 10 MHz sampling frequency.A two-stage OTA with Miller compensation has been de-signed,asshowninFig.4.Thefirststage( - )usesafoldedcascode topology to achieve higher gain, and a common-sourcesecond stage ( - ) is adopted to further increase the gainand to maximize the available output swing. The input andoutput common-mode voltages are set to 250 mV. In advancedCMOS technology, the threshold voltage can be reduced byntsSHEN AND KINGET: A 0.5-V 8-BIT 10-Ms/s PIPELINED ADC IN 90-nm CMOS 791Fig. 3. (a) Standard S/H circuit (all transistors are sized as 12 22m/0.36 22m and C1 is 1pF) and (b) associated node waveforms. (c) Proposed cascaded S/H circuitto combat switch OFF leakage (all transistors are sized as 12 22m/0.3622m, C1 is 1pF, and C2 is 0.25
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