EDA综合设计实验报告

1、EDA综合设计1、七人表决器2、数字抢答器班级：电信一班姓名：马莎莎 学号：2220102802EDA综合设计实验课题一、设计目的 1、掌握用VNDL硬件描述语言做数字电路综合设计的方法。 2、熟练掌握程序的编译、仿真、生成模块及芯片引脚号码锁定方法并下载到目标芯片。二、实验仪器 ZY11EDA13BE型试验箱。三、实验课题 （一）、设计一个七人表决器1、流程图2、顶层原理图3、程序清单 （1）、biaojueqiLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UN

2、SIGNED.ALL;entity biao isport ( xin: in std_logic_vector ( 6 downto 0 ); xout: out std_logic; xout0,xout1: out std_logic_vector ( 6 downto 0 ) ); end entity ;architecture bev of biao isbegin process ( xin ) variable j: integer :=0; begin j:=0; for i in 0 to 6 loop if xin(i)='1' then j:=j+1;

3、end if; end loop;if j>3 then xout<='1' else xout<='0' end if; case j is WHEN 0=>xout1<="1111110" WHEN 1=>xout1<="0110000" WHEN 2=>xout1<="1101101" WHEN 3=>xout1<="1111001" WHEN 4=>xout1<="0110011"

4、; WHEN 5=>xout1<="1011011" WHEN 6=>xout1<="1011111" WHEN 7=>xout1<="1110000" WHEN OTHERS=>xout1<="0000000" end case; case j is WHEN 7=>xout0<="1111110" WHEN 6=>xout0<="0110000" WHEN 5=>xout0<="

5、1101101" WHEN 4=>xout0<="1111001" WHEN 3=>xout0<="0110011" WHEN 2=>xout0<="1011011" WHEN 1=>xout0<="1011111" WHEN 0=>xout0<="1110000" WHEN OTHERS=>xout0<="0000000" end case; end process;end architect

6、ure bev; (2)、mux2LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY mux2 ISPORT( CNTL,CNTH :IN STD_LOGIC_VECTOR(6 DOWNTO 0); CNTOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); SEL:in STD_LOGIC_VECTOR(2 DOWNTO 0);END mux2;ARCHITECTURE BEHAV OF mux2 ISBE

7、GINPROCESS(sel)BEGIN CASE sel IS WHEN"000"=>CNTOUT<=CNTL; WHEN"001"=>CNTOUT<=CNTH; WHEN OTHERS=>CNTOUT<="0000000" END CASE; END PROCESS; END BEHAV;（3）、cnt2LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED

8、.ALL;ENTITY cnt2 ISPORT( CP,RESET:IN STD_LOGIC; SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);END cnt2;ARCHITECTURE BEHAV OF cnt2 ISSIGNAL SEC:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINPROCESS(RESET,CP)BEGIN IF(RESET='0')THEN SEC<="000" ELSIF(CP'EVENT AND CP='1')THEN IF(SEC="001

9、")THEN SEC<="000" ELSE SEC<=SEC+1; END IF; END IF;END PROCESS; SEL<=SEC; END BEHAV;4、仿真波形5、引脚号码锁定分布表实验符号对应附录符号管脚Xin0K1PIN_45Xin1K2PIN_46Xin2K3PIN_47Xin3K4PIN_53Xin4K5PIN_54Xin5K6PIN_55Xin6K7PIN_56Sel0APIN_7Sel1BPIN_8Sel2CPIN_9clk9PIN_79clearK8PIN_57xoutLED16PIN_44Seg0aPIN_10S

10、eg1bPIN_11Seg2 cPIN_12Seg3dPIN_13Seg4ePIN_14Seg5fPIN_15Seg6gPIN_166、生成模块符号（二）、数字抢答器1、设计方框图与 门与门与门检 测保 持电 路号 码显 示电 路控 制电 路计 时电 路计 时显 示抢答状态显示超时状态显示K1K2K3复位开始2、顶层设计原理图3、程序清单 （1）、qiangdajianbelibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity qdjb is port(rst,start,clk2:in s

11、td_logic; s0,s1,s2:in std_logic; states:buffer std_logic_vector(3 downto 0); c0,c1,c2 :buffer std_logic;tmp,q,p:out std_logic);end qdjb;architecture one of qdjb isbeginprocess(s0,rst,start,s1,s2,clk2) begin if rst='0' then q<='0' tmp<='0'states<="0000" elsi

12、f start='0' then p<=s0 or s1 or s2 ; if (s0='1' )then states<="0001" end if ; if (s1='1' ) then states<="0010" end if ; if (s2='1' ) then states<="0011" end if ; elsif clk2'event and clk2='1'and start='1' t

13、hen if (s0='1' )then states<="0001" c0<='1'c1<='0'c2<='0' end if ; if (s1='1' ) then states<="0010" c0<='0'c1<='1'c2<='0' end if ; if (s2='1' ) then states<="0011" c0<=

14、'0'c1<='0'c2<='1' end if ; q<=s0 or s1 or s2 ; tmp<=not(s0 or s1 or s2) ;end if ;end process ;end one;(2)、cnt20library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity CNT20 is port(CLK,EN,CR :in std_logic; co :o

15、ut std_logic; QH,QL:out std_logic_vector(3 downto 0) ); end CNT20; architecture a of CNT20 is signal QNH,QNL :std_logic_vector(3 downto 0); begin co<='1'when(QNL=0 and QNH=0 and EN='1')else'0'process(CLK,CR) begin if(CR='0')then QNH<="0001" QNL<=&qu

16、ot;1001" elsif(CLK'EVENT and CLK='1')then if(EN='1')then if QNL=0 and QNH=0 then QNL<="1001" QNH<="0001" elsif QNL=0 then QNL<="1001" QNH<=QNH-1; else QNl<=QNl-1; end if; end if; end if; end process; QH<=QNH; QL<=QNL; end a;

17、(3)、mux2library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all; entity mux2 is port(in1,in2:in std_logic; sel:in std_logic; q:out std_logic ); end mux2; architecture arc_mux2 of mux2 is begin q<=in1 when sel='0'else in2 when sel='1' e

18、nd arc_mux2;(4)、dongtaisaomiaolibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity sjxz is port (a,b,c: in std_logic_vector(3 downto 0);clk2,rst: in std_logic; s: out std_logic_vector(2 downto 0); y: out std_logic_vector(3 downto 0) ); end sjxz

19、;architecture body_chooser of sjxz is signal count: std_logic_vector (2 downto 0); begin s<=count; process(clk2,rst) begin if(rst='0')then count<="000" elsif(clk2'event and clk2='1')then if(count>="010")then count<="000" else count<=co

20、unt+1; end if;end if;case count is when "000"=>y<=a; when "001"=>y<=b; when "010"=>y<=c; when others=>null; end case; end PROCESS; end body_chooser;(5)、BCDdecoderLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY YMQ IS

21、PORT(AIN4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END YMQ;ARCHITECTURE ART OF YMQ ISBEGIN PROCESS(AIN4) BEGIN CASE AIN4 IS WHEN "0000"=>DOUT7<="1111110" -0 WHEN "0001"=>DOUT7<="0110000" -1 WHEN "0010"=>

22、;DOUT7<="1101101" -2 WHEN "0011"=>DOUT7<="1111001" -3 WHEN "0100"=>DOUT7<="0110011" -4 WHEN "0101"=>DOUT7<="1011011" -5 WHEN "0110"=>DOUT7<="1011111" -6 WHEN "0111"=>DOUT

23、7<="1110000" -7 WHEN "1000"=>DOUT7<="1111111" -8 WHEN "1001"=>DOUT7<="1111011" -9 WHEN OTHERS=>DOUT7<="0000000" END CASE; END PROCESS;END ARCHITECTURE ART;4、仿真波形5、引脚号码锁定分布表实验符号对应附录符号管脚rst1K1PIN_45Rst3K3PIN_47startK2PIN_58S0K5PIN_54S1K6PIN_55S2K7PIN_56Clk19PIN_79Clk27PIN_80Clk38P