超大规模集成电路第四次作业

1、精选优质文档-倾情为你奉上精选优质文档-倾情为你奉上专心-专注-专业专心-专注-专业精选优质文档-倾情为你奉上专心-专注-专业Shown below are buffer-chain designs. Calculate the minimum delay of a chain of inverters for the overall effective fan-out of 64/1. Solution：由题可知：根据经验为最合适的值，所以，所以，但是级数必须为整数所以取，又因为，所以：，所以。(2) Using HSPICE and TSMC 0.18 um CMOS technology

2、 model with 1.8 V power supply, design a circuit simulation scheme to verify them with their correspondent parameters of N, f, and tp.Solution:根据（1）中计算知道三级最合适，所以验证如下：A）、一级无负载测本征延时代码如下：.title buffer-chain 1.lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library.opt scale=0.1u * set

3、lambda.options post=2 list.temp 27.global vdd Vdd vdd gnd 1.8vin vin 0 0.9 pulse 0 1.8 25n 5p 5p 49.99n 100n $频率为10MhzCl vout gnd 0f $Cg1=2.46fF，负载为CL=157.44fF.subckt inv in out wn=3.5 wp=10 t=7.5mn out in gnd gnd NCH l=2 w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out in vdd vdd PCH l=2 w=wp ad=wp*t

4、 pd=wp+2*t as=wp*t ps=wp+2*t.endsX1 vin vout inv wn=3.5 wp=10 t=7.5.op.tran 5p 5n.meas tran voutmax max v(vout) from=5p to=5n.meas tran voutmin min v(vout) from=5p to=5n$一级.meas tran tphl1+trig v(vin) +val=0.9 +rise=1+targ v(vout) +val=0.5*(voutmax-voutmin)+voutmin +fall=1.meas tran tplh1 +trig v(vi

5、n) +val=0.9 +fall=1+targ v(vout) +val=0.5*(voutmax-voutmin)+voutmin +rise=1.end1）一级无负载测得本征延时约为17ps；2）带上64倍Cg1大小的负载测得延时为750.35ps，是本征延时的44倍B）、三级带负载测延时代码如下：.title buffer-chain 3.lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library.opt scale=0.1u * set lambda.options post=2 list.temp

6、 27.global vdd .param fan=4Vdd vdd gnd 1.8vin vin 0 0.9 pulse 0 1.8 25n 5p 5p 49.99n 100nCl vout gnd 0f $Cg1=2.46fF，负载为CL=157.44fF.subckt inv in out wn=3.5 wp=10 t=7.5mn out in gnd gnd NCH l=2 w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out in vdd vdd PCH l=2 w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.

7、endsX1 vin 2 inv wn=3.5 wp=10 t=7.5X2 2 3 inv wn=fan*3.5 wp=fan*10 t=5X3 3 vout inv wn=fan*fan*3.5 wp=fan*fan*10 t=5.op.tran 50p 500n.meas tran voutmax max v(vout) from=50p to=500n.meas tran voutmin min v(vout) from=50p to=500n$三级.meas tran tphl3 +trig v(vin) +val=0.9 +rise=1+targ v(vout) +val=0.5*(

8、voutmax-voutmin)+voutmin +fall=1.meas tran tplh3 +trig v(vin) +val=0.9 +fall=1+targ v(vout) +val=0.5*(voutmax-voutmin)+voutmin +rise=1带上64倍Cg1大小的负载测得延时为174.6ps，是本征延时的10.27倍总结如下：经过调整参数近似时每一级的，所以经过手工计算得到一级带负载和三级带负载的延时比值为：，而仿真得到的结果为，所以符合手工计算的比值，同理其他级的延时代码也是如上的写法，经过仿真得到三级延时最小。.endConsider the logic netw

9、ork below, which may represent the critical path of a more complex logic block. The output of the network is loaded with a capacitance which is 5 times larger than the input capacitance of the first gate, which is a minimum-sized inverter. The effective fanout of the path hence equals F = CL/Cg1 = 5

10、. Using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply, design a circuit simulation scheme to verify the OPTIMAZATION parameters of g, f, and s for each of the inverter and gates.Solution:由题得到路径逻辑努力，由于没有分支B=1，所以，所以使延时最小的逻辑努力为，得到如下的扇出系数：，利用书上公式6.18计算得到尺寸系数。电路仿真代码如下：.title INV 2

11、NAND 2NOR .lib C:synopsysHspice_D-2010.03-SP1tsmc018mm018.l TT * set 0.18um library.options post=2 list.temp 27.global vdd Vdd vdd gnd 1.8vin vin 0 0.9 pulse 0.0 1.8 150p 5p 5p 290p 600pC1 vout gnd 12.3f $Cg1=2.46fF，所以负载为12.3fF.subckt inv1 in out wn=0.35u wp=1u t=0.75umn out in gnd gnd NCH l=0.2u w=

12、wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out in vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.ends.subckt nand3 NAND-A1 NAND-D1 NAND-B1 NAND-C1 wn=0.35u*1.16 wp=1u*1.16t=0.5u $优化尺寸系数S2*.subckt nand3 NAND-A1 NAND-D1 NAND-B1 NAND-C1 wn=0.35u wp=1u t=0.5u $未优化尺寸系数S2mn3 NAND-S2 NAND-C1 gnd

13、 gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmn2 NAND-S1 NAND-B1 NAND-S2 gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmn1 NAND-D1 NAND-A1 NAND-S1 gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp1 NAND-D1 NAND-A1 vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*

14、tmp2 NAND-D1 NAND-B1 vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*tmp3 NAND-D1 NAND-C1 vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.ends.subckt nor2 NOR-A1 NOR-D1 NOR-B1 wn=0.35u*1.34 wp=1u*1.34 t=0.5u $优化尺寸系数S3*.subckt nor2 NOR-A1 NOR-D1 NOR-B1 wn=0.35u wp=1u t=0.5u $未优化

15、尺寸系数S3mn2 NOR-D1 NOR-B1 gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmn1 NOR-D1 NOR-A1 gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp1 NOR-S1 NOR-A1 vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*tmp2 NOR-D1 NOR-B1 NOR-S1 vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t

16、as=wp*t ps=wp+2*t.ends.subckt inv2 in out wn=0.35u*2.6 wp=1u*2.6 t=0.5u $优化尺寸系数S4*.subckt inv2 in out wn=0.35u wp=1u t=0.5u $未优化尺寸系数S4 mn out in gnd gnd NCH l=0.2u w=wn ad=wn*t pd=wn+2*t as=wn*t ps=wn+2*tmp out in vdd vdd PCH l=0.2u w=wp ad=wp*t pd=wp+2*t as=wp*t ps=wp+2*t.endsX1 vin 2 inv1X2 2 3 vd

17、d vdd nand3X3 3 4 gnd nor2X4 4 vout inv2 .op.tran 5p 3000p.meas tran voutmax max v(vout) from=5p to=3000p.meas tran voutmin min v(vout) from=5p to=3000p.meas tran tphl+trig v(vin) +val=0.9 +rise=2+targ v(vout) +val=0.5*(voutmax-voutmin)+voutmin +rise=2.meas tran tplh+trig v(vin) +val=0.9 +fall=2+targ v(vout) +val=0.5*(voutmax-voutmin)+voutmin +fall=2.end$Cg1=2.46fF，所以负载为12.3fF仿真结果如