容错计算英文版课件：lec05-defects

1、Fault-Tolerant ComputingDealing with Low-Level ImpairmentsOct. 20061Defect Avoidance and CircumventionAbout This PresentationEditionReleasedRevisedRevisedFirstOct. 2006This presentation has been prepared for the graduate course ECE 257A (Fault-Tolerant Computing) by Behrooz Parhami, Professor of Ele

2、ctrical and Computer Engineering at University of California, Santa Barbara. The material contained herein can be used freely in classroom teaching or any other educational setting. Unauthorized uses are prohibited. Behrooz ParhamiOct. 20062Defect Avoidance and CircumventionDefect Avoidance and Circ

3、umventionOct. 20063Defect Avoidance and CircumventionOct. 20064Defect Avoidance and CircumventionMultilevel ModelComponentLogicServiceResultInformationSystemLegend:ToleranceEntryOct. 20065Defect Avoidance and CircumventionThe Manufacturing Process for an IC PartOct. 20066Defect Avoidance and Circumv

4、entionThe dramatic decrease in yield with larger dies Effect of Die Size on YieldDie yield =def (Number of good dies) / (Total number of dies) Die yield = Wafer yield 1 + (Defect density Die area) / aa Die cost = (Cost of wafer) / (Total number of dies Die yield) = (Cost of wafer) (Die area / Wafer

5、area) / (Die yield)The parameter a ranges from 3 to 4 for modern CMOS processesShown are some random defects; there are also bulk or clustered defects that affect a large regionOct. 20067Defect Avoidance and CircumventionEffects of Yield on Testing and Part ReliabilityDie yield =assume 50% Out of 2,

6、000,000 dies manufactured, 1,000,000 are defective To achieve the goal of 100 defects per million (DPM) in parts shipped, we must catch 999,900 of the 1,000,000 defective partsTherefore, we need a test coverage of 99.99%Oct. 20068Defect Avoidance and CircumventionExamples of Random Defects in ICsRes

7、istive open due to unfilled via R. Madge et al., IEEE D&T, 2003Particle embedded between layersOct. 20069Defect Avoidance and CircumventionDefect ModelingExtra-material defects are modeled as circular areasPinhole defects are tiny breaches in the dielectricFrom: http:/www.see.ed.ac.uk/research/IMNS/

8、papers/IEE_SMT95_Yield/IEEAbstract.html Oct. 200610Defect Avoidance and CircumventionSensitivity of Layouts to DefectsExtra materialVLSI layout must be done with defect patterns and their impacts in mindA balance must be struck with regard to sensitivity to different defect typesMissing materialActu

9、al photo of a missing-material defect/v3.htm Killer defectLatent defectOct. 200611Defect Avoidance and CircumventionThe Bathtub CurveMany components fail early on because of residual or latent defectsComponents may also wear out due to aging (less so for electronics)In between the two high-mortality

10、 regions lies the useful life periodTimeFailure rateInfant mortalityEnd-of-life wearoutUseful life (low, constant failure rate)MechanicalElectronicPrimarily due to latent defectslOct. 200612Defect Avoidance and CircumventionSurvival Probability of Electronic ComponentsFrom: /hotwire/issue21/hottopic

11、s21.htm Infant mortalityTime in yearsPercent of parts still workingNo significantwear-outOct. 200613Defect Avoidance and CircumventionBurn-In and Stress TestingFrom: /hotwire/issue21/hottopics21.htm Time in yearsPercent of parts still workingBurn-in and stress tests are done in accelerated formDiffi

12、cult to perform on complex and delicate ICs without damaging good partsExpensive “ovens” are requiredOct. 200614Defect Avoidance and CircumventionDefect Avoidance vs. CircumventionDefect AvoidanceDefect awareness in design, particularly layout and routingExtensive quality control during the manufact

13、uring processComprehensive screening, including burn-in and stress testsDefect Circumvention (Removal)Built-in dynamic redundancy on the die or waferIdentification of defective parts (visual inspection, testing, association)Bypassing or reconfiguration via embedded switchesDefect Circumvention (Tole

14、rance)Built-in static redundancy on the die or waferIdentification of defective parts (external test or self-test)Adjustment or tuning of redundant structuresOct. 200615Defect Avoidance and CircumventionDefect Bypassing via ReconfigurationWorks best when the system on die has regular, repetitive str

15、ucture: Memory FPGA Multicore chip CMP (chip multiprocessor)Irregular (random) logic implies greater redundancy due to replication: Replicated structures must not be close to each other They should not be very far either (wiring/switching overhead) Oct. 200616Defect Avoidance and CircumventionPeriph

16、eral reconfiguration elementsDefects in Memory ArraysDefect circumvention (removal)Provide several extra (spare) rows and/or columnsRoute external connections to defect-free rows and columnsSpare rowsSpare rowsMemoryarrayMemoryarrayDefective rowDefectivecolumnDefect circumvention (tolerance)Error-co

17、rrecting codeWith m rows and s spares, can model as m-out-of-(m + s) Somewhat more complex with both spare rows and columns(still combinational, though)Modeling with coded scheme to be discussed at the info levelMethods in use since the 1970s;e.g., IBMs defect-tolerant chipSpare columnsSpare columns

18、Oct. 200617Defect Avoidance and CircumventionYield Improvement in Memory ArraysExample of IBMs experimental 16 Mb memory chipCombines the use of spare rows/columns in memory arrays with ECCFour quadrants, each with 16 spare rows & 24 spare columnsECC corrects any single error via 9 check bits (137 d

19、ata bits)Bits assigned to the same word are separated by 8 bit positionsAvg. number of failing cells per chip40003000200010000100806040200YieldECConlySparesonlyECC and sparesOct. 200618Defect Avoidance and CircumventionDefects in FPGAsDefect circumvention (removal)Provide several extra (spare) CLBs,

20、 I/O blocks, and connectionsRoute external connections to available blocksDefect circumvention (tolerance)Not applicableOct. 200619Defect Avoidance and CircumventionDefects in Multicore Chips or CMPsDefect circumvention (removal)Similar to FPGAs, except that processors are the replacement entitiesIn

21、terprocessor interconnection network is the main challengeWill discuss the switching and reconfiguration aspects in more detail when we get to the malfunction level in our multilevel modelOct. 200620Defect Avoidance and CircumventionCircumventing Defects in Processor ArraysOct. 200621Defect Avoidance and CircumventionDefect Tolerance Schemes for Linear ArraysA linear array with a spare processor and embedded switchingA linear array with a spare processor and reconfiguration switchesOct. 200622Defect Avoidance and CircumventionDefect Tolerance in 2D ArraysTwo types of reconfiguratio