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1、S3C44B0X IIC BUS INTERFACE 李贺超：SC06010056林 健：SC06010031陈小勇：SC06010054SIA-USTCS3C44B0X IIC Bus Interface2OutlineIIC serious bus overviewS3C44B0X IIC bus interface exampleSIA-USTCS3C44B0X IIC Bus Interface3Introduction to IIS bus early 1980s, Philips Semiconductors to provide an easy way to connect a

2、CPU to peripheral chips in a TV-set. to provide a communication link between Integrated Circuits. Inter-IC busintelligent control devices , general-purpose circuits , application-oriented circuits SIA-USTCS3C44B0X IIC Bus Interface4Introduction to IIS bus Today in many other application fieldsaccept

3、ed in the industry as a de-facto standard has been adopted by several leading chip manufacturers like Xicor, Intel, Texas Instruments, Maxim, Atmel, Analog Devices and others. SIA-USTCS3C44B0X IIC Bus Interface5I2C Device CategoriesTV ReceptionRadio ReceptionAudio ProcessingInfrared ControlDTMFLCD d

4、isplay controlClocks/timersGeneral Purpose I/OLED display control Bus Extension/ControlA/D and D/A ConvertersEEPROM/RAMHardware MonitorsMicrocontrollerSIA-USTCS3C44B0X IIC Bus Interface6Appliance can be linkedSIA-USTCS3C44B0X IIC Bus Interface7I2C Bus Speedin the 2001 standard version:Standard; 100k

5、bpsFast mode; 400kbpsHigh speed mode 3.4Mbps HS Mode.Note:While the 2006 version defines the Fast Mode Plus speed grade which increase the bus speed to 1MBps.SIA-USTCS3C44B0X IIC Bus Interface8Pros and Cons of the different busesSIA-USTCS3C44B0X IIC Bus Interface9IIC bus interfaceSIA-USTCS3C44B0X II

6、C Bus Interface10TermsSDA - Serial data line SCL - Serial clock line Transmitter & ReceiverMaster & Slave Multi-masterArbitration SynchronizationSIA-USTCS3C44B0X IIC Bus Interface11I2C Read and Write Operations SIA-USTCS3C44B0X IIC Bus Interface12START and STOP conditions Start: first pulls the SDA

7、(data) line low, and next pulls the SCL (clock) line low. End :The Bus Master first releases the SCL and then the SDA line.SIA-USTCS3C44B0X IIC Bus Interface13Transmitting a byte to a slave Start condition has been sent Transmitted MSB first reserved addresses for special purposes SIA-USTCS3C44B0X I

8、IC Bus Interface14Receiving a byte from a slavethe slave has been addressed , R/W bit set to 1 ,slave has acknowledgedTransmitted MSB firstSIA-USTCS3C44B0X IIC Bus Interface15IIC bus arbitrationthe master who is pulling the line LOW always wins the arbitration Master can start a transfer only if the

9、 bus is free Several masters can start a transfer at the same time Arbitration is done on SDA line while SCL is HIGH ,Slaves are not involvedMaster that lost the arbitration must stop sending data a STOP condition to appear on the bus SIA-USTCS3C44B0X IIC Bus Interface16IIC bus arbitrationSIA-USTCS3

10、C44B0X IIC Bus Interface17Clock Synchronization LOW period determined by the longest clock LOW periodHIGH period determined by shortest clock HIGH periodSIA-USTCS3C44B0X IIC Bus Interface18IIC Special AddressesAddressR/WDesignation0000-0000General Call address 0000-0001START byte 0000-001xReserved f

11、or the (now obsolete) C-Bus format 0000-010 xReserved for a different bus format0000-011xReserved for future purposes 0000-1xxxReserved for future purposes1111-1xxxReserved for future purposes1111-0 xxx 10-bit slave addressing modeSIA-USTCS3C44B0X IIC Bus Interface19Extended Addressing (10-bit)7-bit

12、 address space got exhausted receives two address bytes completely transparent for the other devices on the bus SIA-USTCS3C44B0X IIC Bus Interface20I2C Summary -AdvantagesSimple Hardware standardSimple protocol standardEasy to add / remove functions or devices (hardware and software)Easy to upgrade

13、applicationsSimpler PCB: Only 2 traces required to communicate between devicesSIA-USTCS3C44B0X IIC Bus Interface21I2C Summary -AdvantagesVery convenient for monitoring applicationsFast enough for all “Human Interfaces” applicationsDisplays, Switches, KeyboardsControl, Alarm systemsLarge number of di

14、fferent I2C devices in the semiconductors businessWell known and robust busSIA-USTCS3C44B0X IIC Bus Interface22Standard Philips Copyright notice Purchase of Philips I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conforms to

15、the I2C specifications defined by Philips. SIA-USTCS3C44B0X IIC Bus Interface23OUTLINEIIC serious bus overviewS3C44B0X IIC bus interface ExampleSIA-USTCS3C44B0X IIC Bus Interface24S3C44B0X IIC bus interface 1 Multi-Master IIC-Bus with interrupt-based operation.Serial, 8-bit oriented, bi-directional

16、data transfers can be made at up to 100 Kbps in the standard mode or up to 400 Kbps in the fast mode.60 IICSDA/GPF1(by default)61 IICSCL/GPF0 (by default)SIA-USTCS3C44B0X IIC Bus Interface25Relative registerPCONF 0 x01D20034 PF0 1:0=10(IICSCL) PF1 3:2=10 (IICSDA)CLKCON.13 0 x01D80004 Controls MCLK i

17、nto IIC block 0 = Disable, 1 = Enable (by default)INTPND.5 0 x01E00008 0 = IRQ mode(default),1 = FIQ modeINTMSK.5 0 x01E0000C 0 = Service available 1 = Masked (default)I_PSLV 0 x01E00010IICCON 0 x01d60000 IIC Control 0000_XXXXIICSTAT 0 x01d60004 IIC Status 0000_0000IICADD 0 x01d60008 IIC AddressIICD

18、S 0 x01d6000c IIC Data ShiftSIA-USTCS3C44B0X IIC Bus Interface26IIC-Bus Block DiagramSIA-USTCS3C44B0X IIC Bus Interface27CONTROL REGISTERSIA-USTCS3C44B0X IIC Bus Interface28CONTROL/STATUS REGISTERSIA-USTCS3C44B0X IIC Bus Interface29ADDRESS REGISTERSIA-USTCS3C44B0X IIC Bus Interface30TRANSMIT/RECEIVE

19、 DATA SHIFT REGISTERSIA-USTCS3C44B0X IIC Bus Interface31Operations for Master /Receiver ModeOperations for Master /TransmitterModeSIA-USTCS3C44B0X IIC Bus Interface32Operations for Slave /TransmitterModeOperations for Slave/ ReceiverModeSIA-USTCS3C44B0X IIC Bus Interface33OUTLINEIIC serious bus overviewS3C44B0X IIC bus interface ExampleSIA-USTCS3C44B0X IIC Bus Interface34Examplevoid Test_Iic(vo