MOS集成电路的基本制造工艺

半导体集成电路2022/10/25半导体2022-10-181上节课内容要点双极集成电路的基本工艺双极集成电路中元件结构2022/10/25上节课内容要点双极集成电路的基本工艺2022-10-182pn+n-epin+P-Sin+-BLCBESP+P+双极集成电路的基本工艺2022/10/25pn+n-epin+P-Sin+-BLCBESP+P+双极集3P-SiTepiCBEpn+n-epin+P-SiP+P+Sn+-BLTepiAA’TBL-uptepi-oxxmcxjc四层三结结构的双极晶体管双极集成电路中元件结构2022/10/25P-SiTepiCBEpn+n-epin+P-SiP+P+S4ECB2022/10/25ECB2022-10-185相关知识点隐埋层的作用、电隔离的概念、寄生晶体管2022/10/25相关知识点隐埋层的作用、电隔离的概念、寄生晶体管2022-16本节课内容

MOS集成电路的工艺

P阱CMOS工艺

BiCMOS集成电路的工艺

N阱CMOS工艺双阱CMOS工艺2022/10/25本节课内容MOS集成电路的工艺P阱CMOS工艺7MOS晶体管的动作

MOS晶体管实质上是一种使电流时而流过，时而切断的开关n+n+P型硅基板栅极（金属）绝缘层（SiO2）半导体基板漏极源极N沟MOS晶体管的基本结构源极(S)漏极(D)栅极(G)MOSFET的基本结构2022/10/25MOS晶体管的动作MOS晶体管实质上是一种使n+n+P型8siliconsubstratesourcedraingateoxideoxidetopnitridemetalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongatedopedsiliconfieldoxidegateoxideMOS晶体管的立体结构2022/10/25siliconsubstratesourcedrainga9在硅衬底上制作MOS晶体管siliconsubstrate2022/10/25在硅衬底上制作MOS晶体管siliconsubstrate10siliconsubstrateoxidefieldoxide2022/10/25siliconsubstrateoxidefieldox11siliconsubstrateoxidephotoresist2022/10/25siliconsubstrateoxidephotores12ShadowonphotoresistphotoresistExposedareaofphotoresistChromeplatedglassmaskUltravioletLightsiliconsubstrateoxide2022/10/25Shadowonphotoresistphotoresi13非感光区域siliconsubstrate感光区域oxidephotoresist2022/10/25非感光区域siliconsubstrate感光区域oxid14Shadowonphotoresistsiliconsubstrateoxidephotoresistphotoresist显影2022/10/25Shadowonphotoresistsilicons15siliconsubstrateoxideoxidesiliconsubstratephotoresist腐蚀2022/10/25siliconsubstrateoxideoxidesil16siliconsubstrateoxideoxidesiliconsubstratefieldoxide去胶2022/10/25siliconsubstrateoxideoxidesil17siliconsubstrateoxideoxidegateoxidethinoxidelayer2022/10/25siliconsubstrateoxideoxidegat18siliconsubstrateoxideoxidepolysilicongateoxide2022/10/25siliconsubstrateoxideoxidepol19siliconsubstrateoxideoxidegategateultra-thingateoxidepolysilicongate2022/10/25siliconsubstrateoxideoxidegat20siliconsubstrateoxideoxidegategatephotoresistScanningdirectionofionbeamimplantedionsinactiveregionoftransistorsImplantedionsinphotoresisttoberemovedduringresiststrip.sourcedrainionbeam2022/10/25siliconsubstrateoxideoxidegat21siliconsubstrateoxideoxidegategatesourcedraindopedsilicon2022/10/25siliconsubstrateoxideoxidegat22自对准工艺在有源区上覆盖一层薄氧化层淀积多晶硅，用多晶硅栅极版图刻蚀多晶硅以多晶硅栅极图形为掩膜板，刻蚀氧化膜离子注入2022/10/25自对准工艺在有源区上覆盖一层薄氧化层2022-10-1823siliconsubstratesourcedraingate2022/10/25siliconsubstratesourcedrainga24siliconsubstrategatecontactholesdrainsource2022/10/25siliconsubstrategatecontacth25siliconsubstrategatecontactholesdrainsource2022/10/25siliconsubstrategatecontacth26完整的简单MOS晶体管结构siliconsubstratesourcedraingateoxideoxidetopnitridemetalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongatedopedsiliconfieldoxidegateoxide2022/10/25完整的简单MOS晶体管结构siliconsubstrate27CMOSFETP型sisubn+gateoxiden+gateoxideoxidep+p+2022/10/25CMOSFETP型sisubn+gateoxiden+28主要的CMOS工艺VDDP阱工艺N阱工艺双阱工艺P-P+P+N+N+P+N+VSSVOUTVINVDDN-P+P+N+N+P+N+VSSVOUTVINVDDP-P+P+N+N+P+N+VSSVOUTVINN-SiP-SiN-I-SiN+-Si2022/10/25主要的CMOS工艺VDDP阱工艺N阱工艺双阱工艺P-P+P+29掩膜1：P阱光刻P-wellP-well

N+

N+

P+

P+

N+

P+N-SiP2022/10/25掩膜1：P阱光刻P-wellP-wellN+N+30具体步骤如下：1．生长二氧化硅（湿法氧化）：Si(固体)+2H2OSiO2（固体）+2H22022/10/25具体步骤如下：Si(固体)+2H2OSiO2（固体）31氧化2022/10/25氧化2022-10-18322．P阱光刻：涂胶腌膜对准曝光光源显影2022/10/252．P阱光刻：涂胶腌膜对准曝光光源显影2022-10-18332022/10/252022-10-1834硼掺杂（离子注入）刻蚀（等离子体刻蚀）去胶P+去除氧化膜P-well3．P阱掺杂：2022/10/25硼掺杂（离子注入）刻蚀（等离子体刻蚀）去胶P+去除氧化膜P-352022/10/252022-10-1836离子源高压电源电流积分器离子束2022/10/25离子源高压电流离子束2022-10-1837掩膜2：光刻有源区有源区：nMOS、PMOS

晶体管形成的区域P+N+N+P+N-SiP-wellP-wellP-well淀积氮化硅光刻有源区场区氧化去除有源区氮化硅及二氧化硅SiO2隔离岛2022/10/25掩膜2：光刻有源区有源区：nMOS、PMOSP+N+N+38有源区depositednitridelayer有源区光刻板N型p型MOS制作区域(漏-栅-源)2022/10/25有源区deposited有源区光刻板2022-10-1839P-well1.淀积氮化硅：氧化膜生长（湿法氧化）P-well氮化膜生长P-well涂胶P-well对版曝光有源区光刻板2.光刻有源区：2022/10/25P-well1.淀积氮化硅：氧化膜生长（湿法氧化）P-we40P-well显影P-well氮化硅刻蚀去胶3.场区氧化：P-well场区氧化（湿法氧化）P-well去除氮化硅薄膜及有源区SiO22022/10/25P-well显影P-well氮化硅刻蚀去胶3.场区氧化：P41掩膜3：光刻多晶硅P-well去除氮化硅薄膜及有源区SiO2P-wellP+N+N+P+N-SiP-well栅极氧化膜多晶硅栅极生长栅极氧化膜淀积多晶硅光刻多晶硅2022/10/25掩膜3：光刻多晶硅P-well去除氮化硅薄膜及有源区Si42P-well生长栅极氧化膜P-well淀积多晶硅P-well涂胶光刻多晶硅光刻板P-well多晶硅刻蚀2022/10/25P-well生长栅极氧化膜P-well淀积多晶硅P-well43掩膜4

：P+区光刻

1、P+区光刻

2、离子注入B+，栅区有多晶硅做掩蔽，称为硅栅自对准工艺。

3、去胶P-wellP+N+N+P+N-SiP-wellP-wellP+P+2022/10/25掩膜4：P+区光刻1、P+区光刻P-wellP+44P-wellP+P-wellP+P+硼离子注入去胶2022/10/25P-wellP+P-wellP+P+硼离子注入去胶2022-45掩膜5

：N+区光刻

1、N+区光刻

2、离子注入P+，栅区有多晶硅做掩蔽，称为硅栅自对准工艺。

3、去胶P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+2022/10/25掩膜5：N+区光刻1、N+区光刻P-wellP+46P-wellN+P-wellP+P+磷离子注入去胶P+P+N+N+2022/10/25P-wellN+P-wellP+P+磷离子注入去胶P+P+N47掩膜6

：光刻接触孔1、淀积PSG.2、光刻接触孔3、刻蚀接触孔P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+磷硅玻璃（PSG)2022/10/25掩膜6：光刻接触孔1、淀积PSG.P-wellP+N+N48掩膜6

：光刻接触孔P-wellP+P+N+N+淀积PSGP-wellP+P+N+N+光刻接触孔P-wellP+P+N+N+刻蚀接触孔P-wellP+P+N+N+去胶2022/10/25掩膜6：光刻接触孔P-wellP+P+N+N+淀积PSG492022/10/252022-10-1850掩膜7

：光刻铝线1、淀积铝.2、光刻铝3、去胶P-wellP-wellP+P+N+N+2022/10/25掩膜7：光刻铝线1、淀积铝.P-wellP-wellP+51P-wellP+P+N+N+铝线PSG场氧栅极氧化膜P+区P-wellN-型硅极板多晶硅N+区2022/10/25P-wellP+P+N+N+铝线PSG场氧栅极氧化膜P+区P52Example:Intel0.25micronProcess5metallayersTi/Al-Cu/Ti/TiNPolysilicondielectric2022/10/25Example:Intel0.25micronPro53InterconnectImpactonChip2022/10/25InterconnectImpactonChip20254掩膜8

：刻钝化孔CircuitPADCHIP2022/10/25掩膜8：刻钝化孔CircuitPADCHIP2022-1055双阱标准CMOS工艺P+p-epipwellnwellp+n+gateoxideAl(Cu)tungstenSiO2SiO2TiSi2fieldoxide增加器件密度防止寄生晶体管效应（闩锁效应）2022/10/25双阱标准CMOS工艺P+p-epipwellnwellp56p-epiP阱n+STITiSi2STI深亚微米CMOS晶体管结构STISTISTIN阱n-n+n-p+p-p+p-源/漏扩展区浅槽隔离侧墙多晶硅硅化物2022/10/25p-epiP阱n+STITiSi2STI深亚微米CMOS晶体57功耗驱动能力CMOS双极型Bi-CMOSBiCMOS集成电路工艺2022/10/25功耗驱动能力CMOS双极型Bi-CMOSBiCMOS集成电路58BiCMOS工艺分类以CMOS工艺为基础的BiCMOS工艺以双极工艺为基础的BiCMOS工艺。2022/10/25BiCMOS工艺分类以CMOS工艺为基础的BiCMOS工艺259以P阱CMOS工艺为基础的BiCMOS工艺NPN晶体管电流增益小；集电极的串联电阻很大;NPN管C极只能接固定电位，从而限制了NPN管的使用2022/10/25以P阱CMOS工艺为基础的BiCMOS工艺NPN晶体管电流增60以N阱CMOS工艺为基础的BiCMOS工艺NPN具有较薄的基区，提高了其性能；N阱使得NPN管C极与衬底隔开，可根据电路需要接电位集电极串联电阻还是太大，影响双极器件的驱动能力在现有N阱CMOS工艺上增加一块掩膜板2022/10/25以N阱CMOS工艺为基础的BiCMOS工艺NPN具有较薄的基61

以N阱CMOS工艺为基础的改进BiCMOS工艺使NPN管的集电极串联电阻减小56倍；使CMOS器件的抗闩锁性能大大提高2022/10/25以N阱CMOS工艺为基础的改进BiCMOS工艺使N62三、后部封装（在另外厂房）（1）背面减薄（2）切片（3）粘片（4）压焊：金丝球焊（5）切筋（6）整形（7）密封（8）沾锡：保证管脚的电学接触（9）老化（10）成测（11）打印、包装2022/10/25三、后部封装（在另外厂房）2022-10-1863金丝劈加热压焊2022/10/25金丝劈加热压焊2022-10-1864三、后部封装（在另外厂房）2022/10/25三、后部封装（在另外厂房）2022-10-18652022/10/252022-10-1866作业：1.课本P14，1.2题2.下图是NMOS晶体管的立体结构图，请标出各区域名称及掺杂类型，并画出这个器件的版图（包括接触孔和金属线）。3.名词解释：MOSNMOSPMOSCMOS场氧、有源区、硅栅自对准工艺2022/10/25作业：1.课本P14，1.2题2.下图是NMOS晶体管67半导体集成电路2022/10/25半导体2022-10-1868上节课内容要点双极集成电路的基本工艺双极集成电路中元件结构2022/10/25上节课内容要点双极集成电路的基本工艺2022-10-1869pn+n-epin+P-Sin+-BLCBESP+P+双极集成电路的基本工艺2022/10/25pn+n-epin+P-Sin+-BLCBESP+P+双极集70P-SiTepiCBEpn+n-epin+P-SiP+P+Sn+-BLTepiAA’TBL-uptepi-oxxmcxjc四层三结结构的双极晶体管双极集成电路中元件结构2022/10/25P-SiTepiCBEpn+n-epin+P-SiP+P+S71ECB2022/10/25ECB2022-10-1872相关知识点隐埋层的作用、电隔离的概念、寄生晶体管2022/10/25相关知识点隐埋层的作用、电隔离的概念、寄生晶体管2022-173本节课内容

MOS集成电路的工艺

P阱CMOS工艺

BiCMOS集成电路的工艺

N阱CMOS工艺双阱CMOS工艺2022/10/25本节课内容MOS集成电路的工艺P阱CMOS工艺74MOS晶体管的动作

MOS晶体管实质上是一种使电流时而流过，时而切断的开关n+n+P型硅基板栅极（金属）绝缘层（SiO2）半导体基板漏极源极N沟MOS晶体管的基本结构源极(S)漏极(D)栅极(G)MOSFET的基本结构2022/10/25MOS晶体管的动作MOS晶体管实质上是一种使n+n+P型75siliconsubstratesourcedraingateoxideoxidetopnitridemetalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongatedopedsiliconfieldoxidegateoxideMOS晶体管的立体结构2022/10/25siliconsubstratesourcedrainga76在硅衬底上制作MOS晶体管siliconsubstrate2022/10/25在硅衬底上制作MOS晶体管siliconsubstrate77siliconsubstrateoxidefieldoxide2022/10/25siliconsubstrateoxidefieldox78siliconsubstrateoxidephotoresist2022/10/25siliconsubstrateoxidephotores79ShadowonphotoresistphotoresistExposedareaofphotoresistChromeplatedglassmaskUltravioletLightsiliconsubstrateoxide2022/10/25Shadowonphotoresistphotoresi80非感光区域siliconsubstrate感光区域oxidephotoresist2022/10/25非感光区域siliconsubstrate感光区域oxid81Shadowonphotoresistsiliconsubstrateoxidephotoresistphotoresist显影2022/10/25Shadowonphotoresistsilicons82siliconsubstrateoxideoxidesiliconsubstratephotoresist腐蚀2022/10/25siliconsubstrateoxideoxidesil83siliconsubstrateoxideoxidesiliconsubstratefieldoxide去胶2022/10/25siliconsubstrateoxideoxidesil84siliconsubstrateoxideoxidegateoxidethinoxidelayer2022/10/25siliconsubstrateoxideoxidegat85siliconsubstrateoxideoxidepolysilicongateoxide2022/10/25siliconsubstrateoxideoxidepol86siliconsubstrateoxideoxidegategateultra-thingateoxidepolysilicongate2022/10/25siliconsubstrateoxideoxidegat87siliconsubstrateoxideoxidegategatephotoresistScanningdirectionofionbeamimplantedionsinactiveregionoftransistorsImplantedionsinphotoresisttoberemovedduringresiststrip.sourcedrainionbeam2022/10/25siliconsubstrateoxideoxidegat88siliconsubstrateoxideoxidegategatesourcedraindopedsilicon2022/10/25siliconsubstrateoxideoxidegat89自对准工艺在有源区上覆盖一层薄氧化层淀积多晶硅，用多晶硅栅极版图刻蚀多晶硅以多晶硅栅极图形为掩膜板，刻蚀氧化膜离子注入2022/10/25自对准工艺在有源区上覆盖一层薄氧化层2022-10-1890siliconsubstratesourcedraingate2022/10/25siliconsubstratesourcedrainga91siliconsubstrategatecontactholesdrainsource2022/10/25siliconsubstrategatecontacth92siliconsubstrategatecontactholesdrainsource2022/10/25siliconsubstrategatecontacth93完整的简单MOS晶体管结构siliconsubstratesourcedraingateoxideoxidetopnitridemetalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongatedopedsiliconfieldoxidegateoxide2022/10/25完整的简单MOS晶体管结构siliconsubstrate94CMOSFETP型sisubn+gateoxiden+gateoxideoxidep+p+2022/10/25CMOSFETP型sisubn+gateoxiden+95主要的CMOS工艺VDDP阱工艺N阱工艺双阱工艺P-P+P+N+N+P+N+VSSVOUTVINVDDN-P+P+N+N+P+N+VSSVOUTVINVDDP-P+P+N+N+P+N+VSSVOUTVINN-SiP-SiN-I-SiN+-Si2022/10/25主要的CMOS工艺VDDP阱工艺N阱工艺双阱工艺P-P+P+96掩膜1：P阱光刻P-wellP-well

N+

N+

P+

P+

N+

P+N-SiP2022/10/25掩膜1：P阱光刻P-wellP-wellN+N+97具体步骤如下：1．生长二氧化硅（湿法氧化）：Si(固体)+2H2OSiO2（固体）+2H22022/10/25具体步骤如下：Si(固体)+2H2OSiO2（固体）98氧化2022/10/25氧化2022-10-18992．P阱光刻：涂胶腌膜对准曝光光源显影2022/10/252．P阱光刻：涂胶腌膜对准曝光光源显影2022-10-181002022/10/252022-10-18101硼掺杂（离子注入）刻蚀（等离子体刻蚀）去胶P+去除氧化膜P-well3．P阱掺杂：2022/10/25硼掺杂（离子注入）刻蚀（等离子体刻蚀）去胶P+去除氧化膜P-1022022/10/252022-10-18103离子源高压电源电流积分器离子束2022/10/25离子源高压电流离子束2022-10-18104掩膜2：光刻有源区有源区：nMOS、PMOS

晶体管形成的区域P+N+N+P+N-SiP-wellP-wellP-well淀积氮化硅光刻有源区场区氧化去除有源区氮化硅及二氧化硅SiO2隔离岛2022/10/25掩膜2：光刻有源区有源区：nMOS、PMOSP+N+N+105有源区depositednitridelayer有源区光刻板N型p型MOS制作区域(漏-栅-源)2022/10/25有源区deposited有源区光刻板2022-10-18106P-well1.淀积氮化硅：氧化膜生长（湿法氧化）P-well氮化膜生长P-well涂胶P-well对版曝光有源区光刻板2.光刻有源区：2022/10/25P-well1.淀积氮化硅：氧化膜生长（湿法氧化）P-we107P-well显影P-well氮化硅刻蚀去胶3.场区氧化：P-well场区氧化（湿法氧化）P-well去除氮化硅薄膜及有源区SiO22022/10/25P-well显影P-well氮化硅刻蚀去胶3.场区氧化：P108掩膜3：光刻多晶硅P-well去除氮化硅薄膜及有源区SiO2P-wellP+N+N+P+N-SiP-well栅极氧化膜多晶硅栅极生长栅极氧化膜淀积多晶硅光刻多晶硅2022/10/25掩膜3：光刻多晶硅P-well去除氮化硅薄膜及有源区Si109P-well生长栅极氧化膜P-well淀积多晶硅P-well涂胶光刻多晶硅光刻板P-well多晶硅刻蚀2022/10/25P-well生长栅极氧化膜P-well淀积多晶硅P-well110掩膜4

：P+区光刻

1、P+区光刻

2、离子注入B+，栅区有多晶硅做掩蔽，称为硅栅自对准工艺。

3、去胶P-wellP+N+N+P+N-SiP-wellP-wellP+P+2022/10/25掩膜4：P+区光刻1、P+区光刻P-wellP+111P-wellP+P-wellP+P+硼离子注入去胶2022/10/25P-wellP+P-wellP+P+硼离子注入去胶2022-112掩膜5

：N+区光刻

1、N+区光刻

2、离子注入P+，栅区有多晶硅做掩蔽，称为硅栅自对准工艺。

3、去胶P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+2022/10/25掩膜5：N+区光刻1、N+区光刻P-wellP+113P-wellN+P-wellP+P+磷离子注入去胶P+P+N+N+2022/10/25P-wellN+P-wellP+P+磷离子注入去胶P+P+N114掩膜6

：光刻接触孔1、淀积PSG.2、光刻接触孔3、刻蚀接触孔P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+磷硅玻璃（PSG)2022/10/25掩膜6：光刻接触孔1、淀积PSG.P-wellP+N+N115掩膜6

：光刻接触孔P-wellP+P+N+N+淀积PSGP-wellP+P+N+N+光刻接触孔P-wellP+P+N+N+刻蚀接触孔P-wellP+P+N+N+去胶2022/10/25掩膜6：光刻接触孔P-wellP+P+N+N+淀积PSG1162022/10/252022-10-18117掩膜7

：光刻铝线1、淀积铝.2、光刻铝3、去胶P-wellP-wellP+P+N+N+2022/10/25掩膜7：光刻铝线1、淀积铝.P-wellP-wellP+118P-wellP+P+N+N+铝线PSG场氧栅极氧化膜P+区P-wellN-型硅极板多晶硅N+区2022/10/25P-wellP+P+N+N+铝线PSG场氧栅极氧化膜P+区P119Example:Intel0.25micronProcess5metallayersTi/Al-Cu/Ti/TiNPolysilicondielectric2022/10/25Example:Intel0.25micronPro120InterconnectImpact