VLSI超大规模集成电路：timing

TimingSynchronousTimingTimingDefinitionsRegisterParametersDClkQDQClktc-qtholdTtsuDelayscanbedifferentforrisingandfallingdatatransitionsClockUncertaintiesSourcesofclockuncertaintyClockNonidealitiesClockskewSpatialvariationintemporallyequivalentclockedges;deterministic+random,tSKClockjitterTemporalvariationsinconsecutiveedgesoftheclocksignal;modulation+randomnoiseCycle-to-cycle(short-term)tJSLongtermtJLClockSkewandJitterBothskewandjitteraffecttheeffectivecycletimeOnlyskewaffectstheracemarginClkClktSKtJSPositiveandNegativeSkewPositiveSkewLaunchingedgearrivesbeforethereceivingedgeNegativeSkewReceivingedgearrivesbeforethelaunchingedgeTimingConstraintsMinimumcycletime:T-=tc-q+tsu+tlogicWorstcaseiswhenreceivingedgearrivesearly(positive)TimingConstraintsHoldtimeconstraint:t(c-q,cd)+t(logic,cd)>thold+Worstcaseiswhenreceivingedgearriveslate

RacebetweendataandclockImpactofJitterLongestLogicPathClkTTSUTClk-QTLMLatestpoint

oflaunchingEarliestarrival

ofnextcycleTJI+dClockConstraintsIflaunchingedgeislateandreceivingedgeisearly,thedatawillnotbetoolateif:MinimumcycletimeisdeterminedbythemaximumdelaysthroughthelogicTc-q+TLM+TSU<T–TJI,1–TJI,2-dTc-q+TLM+TSU+d+2TJI<TSkewcanbeeitherpositiveornegativeShortestPathClkTClk-QTLmEarliestpoint

oflaunchingDatamustnotarrive

beforethistimeClkTHNominal

clockedgeClockConstraintsMinimumlogicdelayIflaunchingedgeisearlyandreceivingedgeislate:Tc-q+TLM–TJI,1<TH+TJI,2+dTc-q+TLM<TH+2TJI+dTimingPathStartpoint:

HCLKEndpoint:

bus_hgrant_r_reg/DTcq=?Tsu=?Tj+Ts=?T=?ClockGeneratorQuartzCrystal振荡电路StartupWhyRF?PLLBlockDiagramDCO的结构T2DPhaseDetectorOutputbeforefilteringTransfer

characteristicQuiz哪些因素会导致Jitter?为何不能在芯片内部产生时钟？ClockDistributionHowtocounterClockSkew?ClockDistributionClockisdistributedinatree-likefashionH-treeMorerealisticH-treeTheGridSystemNorc-matchingLargepower2Phase,withmultipleconditionalbufferedclocks2.8nFclockload40cmfinaldriverwidthLocalclockscanbegated“off”tosavepowerReducedload/skewReducedthermalissuesMultipleclockscomplicateracecheckingtrise=0.35nstskew=50pstcycle=1.67nsEV6(Alpha21264)Clocking600MHz–0.35micronCMOSGlobalclockwaveformEV6ClockResultsGCLKSkew(atVdd/2