主板及各类io时钟发生器

PAGE

1

MDS670-02C

Revision050203

ICS670-02

LowPhaseNoise,ZeroDelayBufferandMultiplier

Description

TheICS670-02isahighspeed,lowphasenoise,ZeroDelayBuffer(ZDB)whichintegratesICS’proprietaryog/digitalPhaseLockedLoop(PLL)techniques.PartofICS’ClockBlocksTMfamily,thepart’szerodelayfeaturemeansthattherisingedgeoftheinputclockalignswiththerisingedgesoftheoutputsgivingtheappearanceofnodelaythroughthedevice.Therearetwoidenticaloutputsonthechip.TheFBCLKshouldbeusedtoconnecttotheFBIN.Eachoutputhasitsownoutputenablepin.

TheICS670-02isidealforsynchronizingoutputsinalargevarietyofsystems,from alcomputerstodommunicationsto .Byallowingoff-chipfeedbackpaths,thechipcaneliminatethedelaythroughotherdevices.The15differenton-chipmultipliersworkinavarietyofapplications.Forothermultipliers,includingfunctionalmultipliers,seetheICS527.

BlockDiagram

Features

Packagedin16pinSOIC

Clockoutputsfrom5to160MHz(seepage2)

PatentedPLLwithlowphasenoise

Outputclocksupto160MHzat3.3V

15selectableon-chipmultipliers

Powerdownmodeavailable

Lowphasenoise:-124dBc/Hzat10kHz

Outputenablefunctiontri-statesoutputs

Lowjitter15psonesigma

Advanced,lowpower,sub-micronCMOSprocess

Operatingvoltageof3.3Vor5V

ICLK

VDD

OE1

3

4

GND

OE2

3

DividebyN

VoltageControlledOscillator

PhaseDetector,Charge

Pump,andLoopFilter

FBCLK

FBIN

CLK2

S3:S0

ExternalFeedbackfromFBCLKis mended.

ICS670-02

LowPhaseNoise,ZeroDelayBufferand

MDS670-02C

PAGE

2

Revision050203

PinAssignment MultiplierSelectTable

VDD

1

16

GND

VDD

2

15

GND

VDD

3

14

GND

CLK2

4

13

S0

OE2

5

12

S1

FBCLK

6

11

S2

OE1

7

10

S3

FBIN

8

9

ICLK

S3

S2

S1

S0

CLK2(andFBCLK)

InputRange(MHz)

0

0

0

0

Low(Powerdownentirechip)

-

0

0

0

1

Inputx1.333

18-120

0

0

1

0

Inputx6

5-26.67

0

0

1

1

Inputx1.5

16.67-107

0

1

0

0

Inputx3.333

7.5-48

0

1

0

1

Inputx2.50

10-64

0

1

1

0

Inputx4

6-40

0

1

1

1

Inputx1

25-160

1

0

0

0

Inputx2.333

11-69

1

0

0

1

Inputx2.666

10-60

1

0

1

0

Inputx12

5-13.33

1

0

1

1

Inputx3

8-53.33

1

1

0

0

Inputx10

5-16

1

1

0

1

Inputx5

6-32

1

1

1

0

Inputx8

5-20

1

1

1

1

Inputx2

12-80

PinDescriptions

PinNumber

PinName

PinType

PinDescription

1-3

VDD

Input

Powersupply.Connectbothpinstothesamevoltage(either3.3Vor5V).

4

CLK2

Output

ClockoutputfromVCO.Outputfrequencyequalstheinputfrequencytimesmultiplier.

5

OE2

Input

Outputclockenable2.Tri-statestheclock2outputwhenlow.

6

FBCLK

Output

ClockoutputfromVCO.Outputfrequencyequalstheinputfrequencytimesmultiplier.

7

OE1

Input

Outputclockenable1.Tri-statesthefeedbackclockoutputwhenlow.

9

ICLK

Input

Clockinput.Connecttoa5-210MHzclock.

10

S3

Input

Multiplierselectpin3.Determinesoutputspertableabove.Internalpull-up.

11

S2

Input

Multiplierselectpin2.Determinesoutputspertableabove.Internalpull-up.

12

S1

Input

Multiplierselectpin1.Determinesoutputspertableabove.Internalpull-up.

13

S0

Input

Multiplierselectpin0.Determinesoutputspertableabove.Internalpull-up.

14-16

GND

Power

Connecttoground.

ExternalComponents

TheICS670-02requiresaminimumnumberofexternalcomponentsforproperoperation.Decouplingcapacitorsof0.01mFshouldbeconnectedbetweenVDDandGNDonpins4and5,andVDDandGNDonpins13and12,asclosetothedeviceaspossible.Aseriesterminationresistorof33Wmaybeusedtoeachclockoutputpintoreducereflections.

AbsoluteumRatings

StressesabovetheratingslistedbelowcancausepermanentdamagetotheICS670-02.Theseratings,whicharestandardvaluesforICScommerciallyratedparts,arestressratingsonly.Functionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionsofthespecificationsisnotimplied.Exposuretoabsoluteumratingconditionsforextendedperiodscanaffectproductreliability.Electricalparametersareguaranteedonlyoverthe mendedoperatingtemperaturerange.

Item

Rating

SupplyVoltage,VDD

7V

AllInputsandOutputs

-0.5VtoVDD+0.5V

AmbientOperatingTemperature

0to+70C

StorageTemperature

-65to+150C

JunctionTemperature

150C

SolderingTemperature

260C

mendedOperationConditions

Parameter

Min.

Typ.

Max.

Units

AmbientOperatingTemperature

0

+70

C

PowerSupplyVoltage(measuredinrespecttoGND)

+3.0

+5.5

V

DCElectricalCharacteristics

VDD=3.3V±10%,Ambienttemperature-40to+85C,unlessstatedotherwise

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

OperatingVoltage

VDD

3.0

5.5

V

InputHighVoltage

VIH

2

V

InputLowVoltage

VIL

0.8

V

OutputHighVoltage

VOH

IOH=-12mA

2.4

V

OutputLowVoltage

VOL

IOL=12mA

0.4

V

OutputHighVoltage,CMOSlevel

VOH

IOH=-4mA

VDD-0.4

V

OperatingSupplyCurrent

IDD

NoLoad

35

mA

ICS670-02

LowPhaseNoise,ZeroDelayBufferand

MDS670-02C

PAGE

4

Revision050203

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

ShortCircuitCurrent

IOS

Eachoutput

±50

mA

InternalPull-upResistor

RPU

OE,selectpins

200

k

InputCapacitance

CIN

OE,selectpins

5

pF

ACElectricalCharacteristics

VDD=3.3V±10%,AmbientTemperature-40to+85C,unlessstatedotherwise

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

InputClockFrequency

fIN

Seetableonpage2

5

160

MHz

OutputClockFrequency

160

MHz

OutputRiseTime

tOR

0.8to2.0V,noload

1.5

ns

OutputFallTime

tOF

2.0to0.8V,noload

1.5

ns

OutputClockDutyCycle

tDC

measuredatVDD/2

45

50

55

%

InputtoOutputSkew

Note1

±100

ps

umAbsoluteJitter

shortterm

±45

ps

umJitter

onesigma

15

ps

PhaseNoise,relativetocarrier,125MHz(x5)

100Hzoffset

-110

dBc/Hz

1kHzoffset

-122

dBc/Hz

10kHz

-121

dBc/Hz

200kHz

-117

dBc/Hz

Note1:RisingedgeofICLKcomparedwithrisingedgeofCLK2,withFBCLKconnectedtoFBIN,and15pFloadonCLK2.Seegraphonpage5forskewvs.frequencyandloading.

ThermalCharacteristics

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

ThermalJunctiontoAmbient

JA

Stillair

120

C/W

JA

1m/sairflow

115

C/W

JA

3m/sairflow

105

C/W

ThermalJunctiontoCase

JC

58

C/W

300

200

100

0

-100

-200

-300

-400

25

50

75

100

125

150

CLK2Frequency(MHz)

Skew(ps)20pF Skew(ps)10pF

Skew(ps)

Figure1.SkewfromICLKtoCLK2,withchangeinloadcapacitance(VDD=3.3V)

AdjustingInput/OutputSkew

ThedatainFigure1canbeusedtoadjustindividualcircuitcharacteristicsandachievetheminimumpossibleskewbetweenICLKandCLK2.Witha125MHzoutput,forexample,havingatotalloadcapacitanceof15pFwillresultinnearlyzeroskewbetweenICLKandCLK2.Notethattheload

capacitanceincludesboardtracecapacitance,inputcapacitanceoftheloadbeingdrivenbytheICS670-03,andanyadditionalcapacitorsconnectedtoCLK2.

Figure2.PhaseNoisefor125MHzoutput,25MHzclockinput(VDD=3.3V)

ICS670Phasenoise

0

-20

-40

L(f)dBc

-60

-80

-100

-120

-140

10.E .E+0 1.E+3 10.E .E+3 1.E+6 10.E+6

offsetfrequency

ICS670-02

LowPhaseNoise,ZeroDelayBufferand

MDS670-02C

PAGE

6

Revision050203

PackageOutlineandPackageDimensions(16pinSOIC,150Mil.NarrowBody)

PackagedimensionsarekeptcurrentwithJEDECPublicationNo.95

E H

12

D

A

A1

-C-

e

B

SEATING

NE

.10(.004)C

Millimeters

Inches

Symbol

Min

Max

Min

Max

A

1.35

1.75

.0532

.0688

A1

0.10

0.25

.0040

.0098

B

0.33

0.51

.013

.020

C

0.19

0.25

.0075

.0098

D

9.80

10.00

.3859

.3937

E

3.80

4.00

.1497

.1574

e

1.27BASIC

0.050BASIC

H

5.80

6.20

.2284

.2440

h

0.25

0.50

.010

.020

L

0.40

1.27

.016

.050

0

8

0

8

16

INDEXAREA

C

L

hx45

OrderingInformation

Part/OrderNumber

Marking

Shippackaging

Package

Temperature

ICS670M