电子信息类英文资料加翻译

SequentialLogicTest1.1INTRODUCTIONThepreviouschapterexaminedmethodsforcreatingsensitizedpathsincombina-tionallogicextendingfromstuck-atfaultsonlogicgatestoobservableoutputs.Wenowattempttocreatetestsforsequentialcircuitswheretheoutputsareafunctionnotjustofpresentinputsbutofpastinputsaswell.Theobjectivewillbethesame:tocreateasensitizedpathfromthepointwhereafaultoccurstoanobservableout-put.However,therearenewfactorsthatmustbetakenintoconsideration.Asensi-tizedpathmustnowbepropagatednotonlythroughlogicoperators,butalsothroughanentirelynewdimension—time.Thetimedimensionmaybediscrete,asinsynchronouslogic,oritmaybecontinuous,asinasynchronouslogic.Thetimedimensionwasignoredwhencreatingtestsforfaultsincombinationallogic.Itwasimplicitlyassumedthattheoutputresponsewouldstabilizebeforebeingmeasuredwithtestequipment,anditwasgenerallyassumedthateachtestpat-ternwasindependentofitspredecessors.Aswillbeseen,theeffectsoftimecannotbeignored,becausethisaddeddimensiongreatlyinfluencestheresultsoftestpat-terngenerationandcancomplicate,byordersofmagnitude,theproblemofcreatingtests.Assumptionsaboutcircuitbehaviormustbecarefullyanalyzedtodeterminethecircumstancesunderwhichtheyprevail.1.2TESTPROBLEMSCAUSEDBYSEQUENTIALLOGICTwofactorscomplicatethetaskofcreatingtestsforsequentiallogic:memoryandcircuitdelay.Insequentialcircuitsthesignalsmustnotonlybelogicallycorrect,butmustalsooccurinthecorrecttimesequencerelativetoothersignals.Thetestprob-lemisfurthercomplicatedbythefactthataberrantbehaviorcanoccurinsequentialcircuitswhenindividualdiscretecomponentsareallfault-freeandconformtotheirmanufacturer’sspecifications.Wefirstconsiderproblemscausedbythepresenceofmemory,andthenweexaminetheeffectsofcircuitdelayonthetestgenerationproblem.1.2.1TheEffectsofMemoryInthefirstchapteritwaspointedoutthat,forcombinationalcircuits,itwaspossible(butnotnecessarilyreasonable)tocreateacompletetestforlogicfaultsbyapplyingallpossiblebinarycombinationstotheinputsofacircuit.That,asweshallsee,isnottrueforcircuitswithmemory.Theymaynotonlyrequiremorethan2tests,butarealsosensitivetotheorderinwhichstimuliareapplied.TestVectorOrderingTheeffectsofmemorycanbeseenfromanalysisofthecross-coupledNANDlatch[cf.Figure2.3(b)].Fourfaultswillbeconsidered,thesebeingtheinputSA1faultsoneachofthetwoNANDgates(numberingisfromtoptobottominthediagram).Allfourpossiblebinarycombinationsareappliedtotheinputsinascendingorder—thatis,inthesequence(Set,Reset)={(0,0),(0,1),(1,0),(1,1)}.Wegetthefollowingresponseforthefault-freecircuit(FF)andthecircuitcorrespondingtoeachofthefourinputSA1faults.InputOutputSetResetFF12340010111011011110000011100011Inthistable,faultnumber2respondstothesequenceofinputvectorswithanoutputresponsethatexactlymatchesthefault-freecircuitresponse.Clearly,thissequenceofinputswillnotdistinguishbetweenthefault-freecircuitandacircuitwithinput2SA1.Thesequenceisnowappliedintheexactoppositeorder.Weget:InputOutputSetResetFF123411??01?100000?01101110010111TheIndeterminateValueWhenthefourinputcombinationsareappliedinreverseorder,questionmarksappearinsometablepositions.Whatistheirsignifi-cance?Toanswerthisquestion,wetakenoteofasituationthatdidnotexistwhendealingonlywithcombinationallogic;thecross-coupledNANDlatchhasmemory.Byvirtueoffeedbackpresentinthecircuit,itisabletorememberthevalueofasig-nalthatwasappliedtothesetinputevenafterthatsignalisremoved.Becauseofthefeedback,neithertheSetnortheResetlineneedbeheldlowanylongerthannecessarytoeffectivelylatchthecircuit.However,whenpowerisfirstappliedtothecircuit,itisnotknownwhatvalueiscontainedinthelatch.Howcancircuitbehaviorbesimulatedwhenitisnotknownwhatvalueiscontainedinitsmemory?Inrealcircuits,memoryelementssuchaslatchesandflip-flopshaveindetermi-natevalueswhenpowerisfirstapplied.Thecontentsoftheseelementsremainindeterminateuntilthelatchorflip-flopiseithersetorresettoaknownvalue.InasimulationmodelthisconditionisimitatedbyinitializingcircuitelementstotheindeterminateXstate.Then,asseeninChapter2,somesignalvaluescandriveaoutputoftheflip-flopattheendofthefirstclockperiodisindeterminatebecausethevalueatthemiddleinputtogate3isinitiallyindeterminate.Itisdrivenbytheflip-flopthathasanindeterminatevalue.AfterasecondclockpulsethevalueatQwillremainatX;henceitmayagreewiththegoodcircuitresponsedespitethepresenceofthefault.Thefallacyliesinassumingcorrectcircuitbehaviorwhensettinguptheflip-flopforthetest.Wedependeduponcorrectbehavioroftheverynetthatweareattemptingtotestwhensettingupatesttodetectafaultonthatnet.Tocorrectlyestablishatest,itisnecessarytoassumeanindeterminatevaluefromtheflip-flop.Then,fromtheD-algorithm,weknowthattheflip-flopmustbedrivenintothe0state,withoutdependingontheinputtogate3thatisdrivenbytheflip-flop.Theflip-flopvaluecanthenbeusedinconjunctionwiththeinputstotestfortheSA1onthelowerinputofgate3.Inthisinstance,wecansetA=C=0,B=1.Thena1canbeclockedintotheflip-flopfromgate2.Thisproducesa0ontheout-putoftheflip-flopwhichcanthenbeusedwiththeassignmentA=B=0toclocka0intotheflip-flop.Now,withQ=0andA=B=C=0,anotherclockcausesDtoappearontheoutputoftheflip-flop.NoticethatinputCwasused,butitwasusedtosetupgate2.IfinputCwerefaultedinsuchawayastoaffectbothgates2and3,thenitcouldnothavebeenusedtosetupthetest.1.2.2TimingConsiderationsUntilnowwehaveassumedthaterroneousbehavioroncircuitoutputswastheresultoflogicfaults.Thosefaultsgenerallresultfromactualphysicaldefectssuchasopensorshorts,orincorrectfabricationsuchasanincorrectconnectionorawrongcomponent.Unfortunately,thisassumption,whileconvenient,isanoversimplifica-tion.Anerrormayindeedbearesultofoneormorelogicfaults,butitmayalsobethecasethatanerroroccursandnoneoftheabovesituationsexists.Defectsexistthatcanpreventanelementfrombehavinginaccordancewithitsspecifications.Faultsthataffecttheperformanceofacircuitarereferredtoaspara-metricfaults,incontrasttothelogicfaultsthathavebeenconsidereduptothispoint.Parametricfaultscanaffectvoltageandcurrentlevels,andtheycanaffectgainandswitchingspeedofacircuit.Parametricfaultsincomponentscanresultfromimproperfabricationorfromdegradationasaconsequenceofanormalagingprocess.Environmentalconditionssuchastemperatureextremes,humidity,ormechanicalvibrationcanacceleratethedegradationprocess.Designoversightscanproducesymptomssimilartoparametricfaults.Designproblemsincludefailuretotakeintoaccountwirelengths,loadingofdevices,inad-equatedecoupling,andfailuretoconsiderworst-caseconditionssuchasmaximumorminimumvoltagesortemperaturesoverwhichadevicemayberequiredtooper-ate.Itispossiblethatnoneofthesefactorsmaycauseanerrorinaparticulardesigninawell-controlledenvironment,andyetanyofthesefactorscandestabilizeacir-cuitthatisoperatingunderadverseconditions.Relativetimingbetweensignalpathsortheabilityofthecircuittodriveothercircuitscouldbeaffected.Intermittenterrorsareparticularlyinsidiousbecauseoftheirratherelusivenature,appearingonlyunderparticularcombinationsofcircumstances.Forexam-ple,alogicboardmaybedesignedfornominalsignaldelayforeachcomponentasasafetymargin.Statistically,thedelaysshouldseldomaccumulatesoastoexceedacriticalthreshold.However,aswithanystatisticalexpectation,therewilloccasion-allybeacircuitthatdoesexceedthemaximumpermissiblevalue.Worsestill,itmayworkwellatnominalvoltagesand/ortemperaturesandfailonlywhenvoltagesand/ortemperaturesstrayfromtheirnominalvalue.Anewboardsubstitutedfortheorig-inalboardmaybeclosertotoleranceandworkwellunderthedegradedvoltageandortemperatureconditions.Theoriginalboardmaythen,whencheckedatadepotoraboardtesterunderidealoperatingconditions,testsatisfactorily.Considertheeffectsoftimingvariationsonthedelayflip-flopofFigure2.7.Cor-rectoperationoftheflip-floprequiresthatthedesignerobserveminimalsetupandholdtimes.IfpropagationdelayalongasignalpathtotheDatainputoftheflip-flopisgreaterthanestimatedbythedesigner,orifparametricfaultsexist,thenthesetuptimerequirementrelativetotheclockmaynotbesatisfied,sotheclockattemptstolatchthesignalwhileitisstillchanging.Problemscanalsooccurifasignalarrivestoosoon.Theholdtimerequirementwillbeviolatedifanewsignalvaluearrivesatthedatainputbeforetheintendedvalueislatchedupintheflip-flop.Thiscanhap-penifoneregisterdirectlyfeedsanotherwithoutanyinterveninglogic.Thatlogicorparametricfaultscancauseerroneousoperationinacircuitiseasytounderstand,butdigitaltestproblemsarefurthercompoundedbythefactthaterrorscanoccurduringoperationofadevicewhenitcomponentsbehaveasintended.Elementsusedinthefabricationofdigitallogiccircuitscontaindelay.Ironically,althoughtechnologistsconstantlytrytocreatefastercircuitsandreducedelay,sequentiallogiccircuitscannotfunctionwithoutdelay;circuitsdependbothoncorrectlogicoperationofcircuitcomponentsandoncorrectrelativetimingofsignalspassingthroughthecircuit.Thisdelaymustbetakenintoaccountwhendesigningandtestingcircuits.SupposetheinverterdrivenbytheDatainputinthegatedlatchcircuitofFigure2.4(b)hasadelayofnnanoseconds.IftheDatainputmakesa0-to-1transi-tionfollowedbya0-to-1transitionontheEnableapproximatelynnanosecondslater,thetwocross-coupledNANDgatesseeaninputof(0,0)foraboutnnanosec-ondsfollowedbyaninputof(1,1).Thisproducesunpredictableresults,aswehaveseenbefore.Theproblemiscausedbythedelayintheinverter.AsolutiontothisproblemistoputabufferinthenoninvertingsignalpathsotheDataandDatasig-nalsreachtheNANDsataboutthesametime.Ineachofthetwocircuitsjustcited,thedelayflip-flopandthelatch,araceexists.Araceisaconditionwhereintwoormoresignalsarechangingsimulta-neouslyinacircuit.Theracemaybecausedbymultiplesimultaneousinputsignalchanges,oritmaybetheresultofasinglesignalchangethatfollowstwoormorepathsfromafanoutpoint.Notethatanytimewehavealatchorflip-flopwehavearacecondition,sincethesedeviceswillalwayshaveatleastoneelementwhosesig-nalbothgoesoutsidethedeviceandfeedsbacktoaninputofthelatchorflip-flop.Racesmayormaynotaffectthebehaviorofacircuit.Acriticalraceexistsifthebehaviorofacircuitdependsontheoutcomeoftherace.Suchracescanproduceunanticipatedandunwantedresults.Hazardscanalsocausesequentialcircuitstobehaveinwaysthatwerenotintended.InSection2.6.4theconsequencesofseveralkindsofhazardswerecon-sidered.Liketimingproblems,hazardscanbeextremelydifficulttodiagnosebecausetheireffectonacircuitmaydependonotherfactors,suchasmarginalvolt-agesoranoperatingtemperaturethatiswithinspecificationbutborderline.Underoptimalconditions,aglitchcausedbyahazardmaynotcontainenoughenergytocausealatchtoswitchstate;butundertheinfluenceofmarginaloperatingcondi-tions,thisglitchmayhavesufficientenergytocausealatchofflip-floptoswitchstates.顺序逻辑测试1.1介绍前一章检查方法在结合创建敏化的路径——从固定逻辑，传统逻辑，扩展逻辑门上的断层,可观察到的输出。我们现在尝试创建测试顺序电路输出一个函数不只是当前输入而且是过去的输入。目的将是相同的:创建一个容易发生故障的点，进行检测。然而,有新的的因素必须加以考虑。一个传播——传播路径不仅通过逻辑操作符,也通过一个全新的空间。时间维度可能是离散的,在同步逻辑,或者它可能是连续的,就像在异步逻辑。时间维度被忽视,当创建测试断层组合逻辑。这是隐含假定输出响应之前会稳定被测量与测试设备,它是通常假定每个测试帕特-燕鸥是独立于其前任。我们可以看到,时间的影响不能被忽略,因为这增加了维度极大地影响了结果的测试帕特-燕鸥生成和可以复杂化,几个数量级的问题,创建测试。假设电路的行为必须加以仔细分析来确定，在何种情况下他们占上风。1.2测试顺序逻辑所引起的问题两个因素建立测试的工作复杂化的顺序逻辑:记忆和电路延迟。在时序电路信号不仅要在逻辑上正确,但是还必须发生在正确的时间序列相对于其他信号。测试问题——对应，当进一步复杂化的异常行为的事实可以发生在顺序电路当个别离散的组件都是绝对没错的,符合他们的要求。我们首先考虑的存在而引起的问题内存,然后我们检查的影响电路测试生成的延迟问题。1.2.1记忆的影响在第一章中指出,组合电路,这是可能的(但不一定是合理的)来创建一个完整的测试逻辑错误通过应用所有可能的二进制组合一个电路的输入。那,正如我们将要看到的,是与记忆并不适用于电路。他们不仅可能需要超过2测试,但是同样也对刺激的顺序应用。测试矢量排序内存的影响可以看到从分析交叉耦合与非门闩。四个缺点将被考虑,这些被输入SA1断层对两个中的每一个与非门盖茨(编号是顶级的的倒数图)。所有四个可能的二进制组合应用于在提升命令输入,在序列(集,重置)={(0,0)、(0,1),(1,0),(1,1)}。我们得到如下的响应的无故障电路(FF)和电路对应每个四个输入SA1缺点。输入输出SetResetFF12340010111011011110000011100011在这个表中,错号码2响应序列的输入向量加上一个输出响应完全匹配电路无故障的响应。显然,这个序列输入不会区分无故障电路和电路输入2SA1。序列是现在应用于完全相反的顺序。我们得到:输入输出SetResetFF123411??01?100000?01101110010111不确定当四个输入值的组合应用于相反的顺序,问号出现在一些表头寸。什么是他们的极其重要的部分？要回答这个问题,我们注意的情况,不存在只涉及与组合逻辑;交叉耦合与非门闩记忆。由于反馈出现在电路,它能够记住一个团体的价值，用于设置输入信号是移除，之后就是这样。由于反馈,无论是设置和重置线需要保持在低水平,任何了更长的时间才能有效地拴住电路。然而,当权力是第一应用于电路,也不知道是什么值包含在门闩。如何模拟电路的行为时,不知道是包含在它的价值是什么记忆吗?在实际电路、内存等元素首次应用必须考虑功率问题。这些元素的内容保持不确定,门闩或触发器被设置或重置为已知值。在一个这种状况是仿真模型所模仿的初始化电路元件不确定的X状态。然后,在第二章中看到,一些信号值可以开车逻辑元素到一个已知状态,尽管存在不确定的值其他投入。例如,在图2.1和登机口(c)响应为0时任何单个输入接收一个0,无论何种值出现在其他输入。然而,如果一个1是应用在所有其他的输入都是在X,输出仍在X。回到门闩,第一个序列开始运用0来两个输入,而第二个序列开始通过应用1s,两个输入。在这两种情况下内部网最初是不确定的。0年代的第一个序列能够开车门闩,一个已知状态,使其能够立即区分正确的和错误的反应之间。当应用模式以相反的顺序,花时间开门闩到一个状态良好的电路反应可能是借给别人应用时因错误的电路响应。结果,只有四分之一的断层检测到,即断层1。电路故障2和3同意良好的电路反应的情况好电路具有一个已知的响应。在第一模式好电路响应的秘密如果振荡做消退,没有可行的方法来预测,从一个逻辑描述的回路,最终的状态门闩落定。因此,与非门输出设置为不确定的X。当我们分析可能检测到故障的有效性的二进制序列应用于与非门闩降序排列的,我们不能索赔确固定逻辑，故障将被发现。幸运的是,故障发现当向量都是应用于升序排列。在其他电路的仍然按原来排列。在图2.4(b)数据输入补充和两个真正的和补充值应用于门闩。除非存在一个缺点,门闩不会振荡。然而,当试图创建一个测试电路,我们遇到另一个问题。如果启用信号SA1,逆变器的输出由使已经0和与非门闪存驱动逆变器是盖茨，永久地在一个1状态;因此指责门闩无法初始化到一个已知的状态。不确定的州被纵火门闩节点开始之前测试模式一代和各州仍然不确定断裂的电路。如果电力用于无故障、断裂插销,电路可能刚好出现在同一个州。这个问题所内在有限状态机(FSM)。这个FSM的特点是一组状态Q={q,q,...,q}一组输入刺激I={i,i,...,i}，另一组Y={y,y,...,y}的输出响应,和一双映射M:Q×I→QZ:Q×I→Y这些映射定义下一状态转换和输出行为作为回应任何一个特定的输入刺激。这些映射假设当前的知识FSM的状态的时候刺激是应用。当最初的刺激应用,状态是未知的,除非一些立的方式(如一个重置的存在驾驶FSM处于一种已知状态。一般来说,如果没有独立意味着初始化一个FSM,如果时钟或使输入是错误的,那么它不可能适用于单个逻辑单元来，FSM和检测存在的故障。一种方法是使用在行业是标记错误,可能是检测电路无故障驱动输出插口到一个已知的逻辑状态和故障原因进行同样的假设一个未知的状态。这个行业并没有完全同意有关的分类proba，检测到故障祝福。有些测试工程师保持这样的错误是可能的最终成为检测到,其他人认为它应该继续划分为未被发现的,还有一些人则倾向于认为,它是一种可能的检测。如果检测到可能故障被标记为检测到,那么有一个问题,可能是设计来测试生成忽略这个错误并不是试图创建一个测试,在这些情况下,一个测试存在。1.2.2初始化问题在模拟语言-标量、电路操作始于D触发器在未知状态。在正常操作,当输入组合一个=B=C=0是应用和触发器是悠悠,问输出切换到0。这个触发器可以记录一次为了获得一个测试输入的较低的3号登机口SA1。如果它是SA1,预期的值Q=1;如果它是绝对没错的,预期的值是Q=0。不幸的是,测试有一个严重的缺点!如果低投入到3号登机口是SA1,触发器的输出结束时的第一个时钟周期是不确定的,因为在中间值输入到3号登机口最初是不确定的。它是由flip——失败,一个不确定的值。在第二个时钟脉冲Q将价值保持在X;因此它可能同意好电路响应尽管存在断层。这个谬论在于假设校正电路时的行为设置触发器的测试。我们依赖的正确行为,我们是非常网试图测试在设立一项测试来检测一个断层对净。正确地建立一个测试,它是必要的假设一个不确定的值这个触发器。然后,从算法中,我们知道必须驱动的触发器到0状态,而不取决于输入。触发器的值就可以结合使用来测试的输入在低投入的SA1的3号登机口。在这个实例中,我们可以设置一个=C=0,B=1。然后一个1可以进入触发器以从门2。这就形成了一个0,-把触发器的就可以用这些用任务A=B=0到钟了0到触发器。现在,随着