DisplayPort-物理层测试的挑战讲课讲稿课件

DisplayPort

Testing

ChallengesDisplayPortTestingChallengesAgenda5/23/13

DisplayPort

Overview

DisplayPort

1.2

updatesDisplayPort1.2

Transmitter

TestingWhat’sNew:T2,TP3,TP3EQPhysical

Layer

TestOverviewfor

DP1.2Manual

measurements/DPOJET/SDLACTLE

required

in

RxDP-AUX:

Control

DUT

parametersControls

ALL

TX.

RX

devices

withoutvendor-specific

control

SWTest

Automation:Full

Main

Linktesting

with

DP12

Automatedtool

setDP

1.2

Tx:Including

Single-Ended

and

DiffMeasurements(Intra-Pair

Skew,ACCommon

Mode)Using

RF

SwitchIntegrationImproved

Debug

ToolsDisplayPortSink/Receiver

TestingBSA125C

configurationstowards

RxtestingJitterImpairmentprofile

and

observationtimes

eDP

testing

for

eDP

1.4

specification

MyDPupdateRef:

VESA®

DisplayPort®

PHY

Compliance

Test

Specification

Version

1.2Agenda5/23/13 DisplayPortOvDisplayPort

–Technology

OverviewDisplayPort

is

expanding

itsfootprint

Standard

DisplayPortSpecification

Version

1.2CTS

Version

1.2bData

Rates

1.62GBps,

2.7Gbps

and

5.4GbpsBoxto

Box

(

1,2,4

lanes)

eDPSpecification

Version

1.4CTG

in

progressData

Rates

1.62GBps,

2.7Gbps

and

5.4GbpsEmbedded(single

box

–

Laptops)

(1,2,4

lanes

MyDPSpecification

Version

1.0CTS

Version

1.0

(in

approval)Data

Rates

1.62GBps,

2.7Gbps

and

5.4GbpsMobiles

(

1

lane)

iDPSpecification

Version

1.1CTGData

Rates

3.24,3.78LVDS

replacement)5/23/13DisplayPort–TechnologyOverviDisplayPort1.2Overview5/23/13

The

DisplayPort

PHY

ComplianceTest

Specification

establishes

atest

regimento

determine

compliance

ofDisplayPort

devices

-

segmented

into:SourceReceiverCopper

CableHybrid

devicesTethered

devices

Test

PointDefinitionsTP1:atthe

pins

ofthetransmitterdevice.TP2:atthetest

interface

on

atest

accessfixtureTP3:atthetest

interface

on

atest

accessTP3_EQ:

TP3

with

equalizer

applied.TP4:atthe

pins

ofa

receiving

deviceDisplayPort1.2Overview5/23/1DisplayPort

CTS1.2bSource

Test

Suite

1.EYE

Diagram

2.Non

Pre-Emphasis

Level

Verification

3.Pre-Emphasis

Level

Verification

and

Maximum

Differen

4.Inter-pair

Skew

5.Intra-Pair

Skew

6.Differential

Transition

Time

7.Single

Ended

Rise

and

Fall

Time

Mismatch

8.Overshootand

UndershootTest

9.Frequency

Accuracy

10.AC

Common

Mode

Noise

11.Non

ISI

Jitter

Measurement

12.Total

Jitter

and

Random

Jitter

Measurement

13.UnitInterval

14.Main

Link

Frequency

Compliance

Stability

15.Spread

Spectrum

Modulation

Frequency

16.Spread

Spectrum

Deviation

17.dF/dt

Spread

Spectrum

Deviation

HF

VariationtialPk-Pk

OutputVoltage

DUT

Configuration1.BitRates:

RBR,HBR

or

HBR22.Patterns:

D10.2,PRBS7,COMP,

PLTPAT,PCTPAT3.FFE

(Pre-Emphasis):

0dB,

3.5dB,

6dB,

9.5dB4.OutputLevels:

400mV,

600mV,

800mV,

1200mV5.SSC

(Spread

Spectrum):

On/Off6.Post-Curser2:Level

0,1,2,37.

LaneWidth,1,2,45/23/13

18.Dual-mode

TMDS

Clock

(ifsupported)

19.Dual-mode

EYE

Diagram

Testing

(ifsupported)DisplayPortCTS1.2b 1.EYEDEye

Diagram

Test

using

Eye

Compliance

PatternAn

Eye

diagramtestfor

800mV,0dB

pre-emphasis

atTP2,TP3,TP3-EQ.5/23/13EyeDiagramTestusingEyeComDisplayPort1.2CTLE

Properties5/23/131.2

CTS

requires

adaptive

application

of

one

of

three

reference

equalizersto

the

far

end

signal,

to

find

a

passing

condition.DisplayPort1.2CTLEPropertieKey

Elements

of

DisplayPort

1.2

Transition:Eye

Diagram/Mask

1.2CTS

Requires

Adaptive

Eye

DiagramFindthe

highest

vertical

eye

pointbetween.375

--.625

UIat10E-9BERAnalyticaltools

which

examinethe

vertical

noise

components

projectthe

Rncomponentsto

10E9

BER.

Thesetools

have

been

proven

inthefield

in

SATA

wherethey

have

been

deployedfor

overtwo

years.5/23/13KeyElementsofDisplayPort1.Key

Elements

of

DisplayPort

1.2

Transition:dFdTWhile

dFdT

measurements

have

a

unique

origin

emergingfromthe

SATA

and

SAS

specifications

wherethe

history

ofexamining

SATA

dFdT

has

ledthisto

become

a

highly

recommend

analysis.

The

dFdT

contributing

components

will

rarely

appear

inthe

normal

Jitter

budgetduetotheir

lowfrequency

nature.5/23/13KeyElementsofDisplayPort1.DisplayPort

Auxiliary

Channel

Controller

(DP-AUX)HPDAux

Channel

Speeds

Up

Test

Time

-

No

UserInteraction

is

Requiredto

Change

Source

OutputSignalor

Validate

Sink

Silicon

State

or

Error

Count

No

Needto

Learn

Vendor-specific

Software

-

A

Single

GUISupports

All

Vendors

View

&

Log

Decoded

AUX

Traffic

and

HotPlug

Detect

(HPD)

Eventsfromthe

Deviceunder

Testtothe

DP-AUX

DisplayPortAUX

Controller

Abilityto

Read

and

Write

DPCD

Registers

Supports

Debug

Activities

Tektronix

DP-AUX

can

serves

as

a

DP1.2

Sink

-

Enables

sourcetotransmitthe

requiredpatternsfortesting.5/23/13Why

use

AUX

channel

controller

in

physical

layertesting?DisplayPortAuxiliaryChannelAutomation:

DisplayPort

testing

is

a

large

task!5/23/13Combination

Parameters

For

DP1.2

TestingDataRateLanesPre-EmphasisVoltage

SwingPost

Cursor2SSCPatterns-

3-

44

Levels4

Levels4

Levels2

Levels(SSC

On

and

Off)5

Supported

PatternsCombination

of

TestsDifferential

TestsSingle

Ended

Tests~432

Acquired

signalsfor

DP1.2

Normative

Measurements

per

lane.X4

lanes

results

in

1728

Automated

Acquisitions

per

DUT.TestWaveforms(SSC,

4

Lanes

Possible

Combinations)Eye

Diagram

Test80Pre-Emphasis

Test240Non-Pre-Emphasis32Total

Jitter80Automation:DisplayPorttestinTekExpress

DisplayPort1.2Automation

Comprehensive

DisplayPort

Version

1.2

Physical

Layer

Conformance

andCompliance

Verification

ToolAll

Core

DP1.2

measurementsKeithley

RF

Switch

and

DP-AUXfully

automated

solution.Selected

measurements

can

beapplied

across

alltest

permutations(SSC,CTLE’s,

swing,rates,

pre-emphasis,

etc.)translatesto

1728

measurements. DP1.2

willprovidefull

user

interventionfree,automatedtesting.This

isthe

killervalue

proposition.Factory

Automation

APIforfullproduct

control

in

silicon

automationsystems.Complimentary

Fixtures

andComplianceInterconnect

ChannelHW

defined

by

VESA

makethispackage

afull

customer

solutionwith

no

compromises.5/23/13TekExpressDisplayPort1.2AutDisplayPort1.2Test

Selection

DP1.2Measurementselection

isnow

provided

as

afunction

ofthe

userspecifiedtesttargetcapabilities.IfPost

Curser

2capabilities

are

notpresentinthe

DUT,themeasurementlist

will

notshowthem.Configurationschematicsand

online

help

availablefor

all

measurements5/23/13DisplayPort1.2TestSelectionDisplayPort1.2Acquisitions

DP1.2Various

signal

interconnect

methods

are

supported.Direct

TCA

(SMA

input)

onuser

selected

channels.Differential

Probe(P7313SMA)

inputsfortrue4

channel

concurrentinterconnect.

(No

singleended

measurements)24:4Keithley

RF

Switchallowsfully

automatedcontrol

ofall

8

single

endedinputsfor

handsfreecomprehensive

testing.

Test

PatternsAutomaticverification

oftest

patterns

(which

can

bedisabled)

ensuresthecorrect

patterns

are

usedforthe

correcttest

undermanual

operation.5/23/13DisplayPort1.2AcquisitionsKeithley

RF

Switch

Integration

and

AutomationDisplayPorttransmitter

has

both

Differentialtests

and

Single

endedtests

and

withthe

integration

ofRF

switch

we

have

complete

automated

solution

withoutanyuser

interventionfor

switching

between

lanes

with

both

single

ended

anddifferentialtests

in

sequential

automated

passes.15Keithleyis

now

part

ofTektronix.5/23/13KeithleyRFSwitchIntegrationDisplayPort1.2User

Preferences

DP1.2User

definedtest

margincontrols

and

autohighlightingof

measurements

within

a

userspecifiedtolerance

ofeitherthe

standard

spec

limits

oruser

defined

custom

limits.Email

controls

allownotification

oftest

conditionsdirectlyto

users.5/23/13DisplayPort1.2UserPreferencDisplayPort1.2Reporting

DP1.2Custom

html

reportswhich

include

userspecified

degrees

ofdetail.Reports

and

Session

rawdata

are

storedtogetherallowing

recalling

aprevious

run

and

re-runningthetest

(withdifferentmeasurementconfigurations

or

limits)and

re-generating

a

newreport,without

the

actual

DUTpresent.5/23/13DisplayPort1.2Reporting DPConventional

DisplayPort

Fixtures

+

CIC

Partnership

with

Wilder

Technologiesto

design

and

channel

high

performanceDP

fixtures

Wilder

TF-DP-TPA-PRCfixtures

and

CIC

andfixturesavailable

directlyfrom

Tektronix5/23/13ConventionalDisplayPortFixtuReceivertesting

is

performed

with

a

Tektronix

BSA125C

BertScope

and

Wilder

HBR2

ISI

Channel. BER

observationtimes

rangefrom

37

secondsto

10.5

minutes

depending

onthe

data

rate

and

jitterfrequency

beingtested.e

version

1.2

CTS

outlines

17

Tx

validationtests

which

aretypically

evaluated

with

a

12.5GHz

or

higher

bandwidth

oscilloscope.DisplayPort1.2Sink

(Rx)

Test

Overview5/23/13ReceivertestingisperformedFour

Principal

Test

Frequencies

at2,10,20

and

100

MHz

SJDisplayPort1.2Sink

(Rx)

Test

Observation

Time205/23/13FourPrincipalTestFrequencieBertScope

Receiver

Test

SolutionTypical

Configuration

BertScope

BSA85C–

Option

STR

DPP125A

(no

4T

needed)

BSA12500ISI

DP-AUX

TF-DP-CIC-C1–

Wilder

DP

1.2

ISI

Board5/23/13BertScopeReceiverTestSolutiTwo

Tone

SJ,

with

Stationary

HFSJ

Parked

at

200

MHz.New

HFSJ

source

forfixed

200

MHz

SJ

asrequired

by

DP1.2.5/23/13TwoToneSJ,withStationaryHDisplayPort1.2Crosstalk

(BUJ)

ConfigurationGenerator

page

showingPatterns

and

capabilityof

generation

largeamount

Crosstalk

withdifferential

sub-rateClock

Outputs.5/23/13DisplayPort1.2GeneratorpageDisplayPort

1.2

-High

end

BeRTScope

configurationToDUT5/23/13DisplayPort1.2-HighendBeRTBSAITS125

generatesmultiple,fixed

selectionsfor

ISI…Use

BERTScope

DPPB

orDPPCto

generate

low

passfiltertofinetune

ISIOn

BSAITS

GUI,you

can

simplydialintheamountofISI

needed…andDPP

andBSAITS

willadjusttogeneraterequested

ISI…2011/10Can

automatecalibration

whenusing

BSAITS

with

DPPCan

preciselytune

ISI

atall

dataratesCan

generateadditional

ISItotest

margin

ofDUTDisplayPort

1.2

-High

end

BeRTScope

configurationBSAITS125generatesmultiple,RBR

ISI

created

using

BSAITS

and

DPP125B2011/10DisplayPort

1.2

-High

end

BeRTScope

configurationRBRISIcreatedusingBSAITSaEmbedded

DisplayPort-eDP

Typical

connection5/23/13EmbeddedDisplayPort-eDPTypiceDP

source

measurements:Test

3.1

-

Eye

Diagram

Test

Test

3.2

-Inter

Pair

SkewtestTest

3.3

-

Non-ISI

Jitter

MeasurementsTest

3.4

-

Total

JitterTest

3.5

-

Deterministic

jitterTest

3.6

-

Random

JitterTest

3.7

-

Main

Link

Frequency

StabilityTest

3.8

-

Spread

Spectrum

Modulation

FrequencyTest

3.9

-

Spread

Spectrum

Modulation

DeviationEmbedded

DisplayPort-eDP5/23/13eDPsourcemeasurements:TestOscilloscope

RequirementsOptionEDP

requires

a

DPO/DSA/MSO

70K

scope

runningfirmware

version6.4.0or

higher

and

DPOJetversion

6.0

or

higher.For

customerstesting

RBR

(1.62

Gb/sec)

and

HBR

(2.7

Gb/sec)

a

minimumbandwidth

of8Ghz

is

required.For

customerstesting

HBR2

(5.4

Gb/sec)

a

minimum

12.5GHz

BW

isrequired.ProbingFor

customerstesting

RBR

(1.62

Gb/sec)

or

HBR

(2.7

Gb/sec)

Qty

4

P7380or

P7380SMA

are

required

iftesting

morethentwo

lanes

atonetime.For

customerstesting

HBR2

(5.4

Gb/sec)

and

HBR

(2.7

Gb/sec)

and

RBR(1.62

Gb/sec)

Qty

4

P7313

or

P7313MA

are

required

iftesting

morethentwo

lanes

atonetime.An

optional

eDP

fixture

is

available

onthe

Tektronix

PAL:TF-EDP-TPA-PRCEmbedded

DisplayPort-eDP5/23/13OscilloscopeRequirementsEmbedEmbedded(eDP)

Fixturing5/23/13

20-Pin

eDP

Connectorfor

CCFL

Backlight(1

or

2

Lane

eDP)

30-Pin

eDP

Connectorfor

LED

Backlightw/o

LED

Driver

on

PCB

(1

or

2

Lane

eDP

30-Pin

eDP

Connectorfor

LED

Backlightwith

LED

Driver

on

PCB

(1

or

2

Lane

eDP

40-Pin

eDP

Connectorfor

LED

Backlightwith

LED

Driver

on

PCB

(upto

4

Lane

eDP)Embedded(eDP)Fixturing5/23/1MyDP-

Typical

connection5/23/13MyDP-Typicalconnection5/23/1MyDP-

PHY

tests

for

Source5/23/13Mosttests

will

be

similarto

standard

DP

1.2

ONE

LANEtestsMyDP-PHYtestsforSource5/23MyDP-

PHY

tests

for

SinkSink

Test

will

be

similarto

standard

DP

1.2

ONE

LANEtestsBSAITS125generatesmultipl